Method and apparatus for placement and routing of analog components
Granted: June 5, 2018
Patent Number:
9990461
A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a…
Routing process including dynamically changing pad sizes
Granted: June 5, 2018
Patent Number:
9990456
The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part,…
Controller, system, and method for re-establishment of common mode in a transmission driver
Granted: May 29, 2018
Patent Number:
9985665
A method, control apparatus, and system for re-establishing a common mode in a transmitter involve switching a driver circuit of the transmitter to a quick charge or quick discharge mode based on an output value of the transmitter. When the output later exceeds a programmable common mode voltage, the driver circuit is switched to a classical margining mode to bring the output back towards the targeted common mode voltage. The modes are switched by adjusting the number of activated…
Methods and apparatuses for a CMOS-based process insensitive current reference circuit
Granted: May 22, 2018
Patent Number:
9977454
Disclosed are apparatuses and methods for implementing CMOS-based, process insensitive current reference circuit(s). An apparatus includes a constant transconductance circuitry including a first and second current mirrors and respectively generating constant currents across one or more process corners, a resistive transistor in the constant transconductance circuitry having a resistance, and a feedback circuitry coupled with the resistive transistor and the constant transconductance…
Boundary scan receiver
Granted: May 8, 2018
Patent Number:
9964593
A system, method, and circuits for processing a boundary scan result involve receiving the boundary scan result as input data to a comparator, and performing a comparison based on the input data and a selected reference level to form a comparison result. A capture device that stores the comparison result is set, reset or write enabled based on the comparison result and a reference value indicating which of two reference levels is the selected reference level. Additionally, a…
Method for closed loop testing of ASICs with image sensors in emulation
Granted: April 17, 2018
Patent Number:
9946831
A system, method, and computer program product for dynamic closed loop testing of an emulated ASIC interfaced to a sensor device. An adapter adjusts non-pre-recorded active sensor device data to be readable by an emulated ASIC design by adjusting data rates and performing formatting per a selected compatible interface. The adapter also adjusts control commands generated by the emulated ASIC design, including those generated in response to received and evaluated sensor device data, to be…
Systems and methods to capture data signals from a dynamic circuit
Granted: April 17, 2018
Patent Number:
9946624
A system for tracing an operation of an electronic circuit is provided. The system includes an electronic circuit, a trace buffer, and a trigger detection circuit. The trace buffer includes a plurality of segments configured to continually collect and store data signals of the electronic circuit. The data signals are collected in a current segment of the plurality of segments. The trigger detection circuit is adapted to provide a trigger signal when a trigger condition is met. Each time…
SerDes alignment process
Granted: April 10, 2018
Patent Number:
9940288
The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more…
System and method for controlling optimized access to memory device having three-dimensional stacked structure
Granted: April 10, 2018
Patent Number:
9940260
A memory controller system optimally controls access to a memory device having a plurality of integrated circuit (IC) chips disposed in a non-uniform stack configuration within a three-dimensional stacked (3DS) structure. A memory profiling portion executes to determine the non-uniform stack configuration. A virtual rank mapping portion configured to assign virtual ranks to chip locations actually defined by the non-uniform stack configuration. An address conversion portion executes to…
Security data path verification
Granted: April 3, 2018
Patent Number:
9934410
A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path…
Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design
Granted: April 3, 2018
Patent Number:
9934354
Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can…
Method and system for automated debugging of a device under test
Granted: March 27, 2018
Patent Number:
9928328
A method for automated debugging of a design under test (DUT), including using a processor, (a) identifying a value of a signal at a specific time instance in which a user has indicated interest; (b) performing driver tracing based on structural analysis and signal analysis to determine one or a plurality of drivers of the identified value in the signal; (c) if the driver tracing returns a single driver of said one or a plurality of drivers, presenting the returned single driver to the…
System and method for accurate modeling of back-miller effect in timing analysis of digital circuits
Granted: March 27, 2018
Patent Number:
9928324
A system, method, and computer program product for modeling a receiver load in static timing analysis of digital circuits. Embodiments separate total receiver charge into static and dynamic components, and extract both from an improved library model. The receiver load is effectively modeled with a static capacitance and a current source connected in parallel. A method of extracting load model characteristics from a standard timing library is also provided. The improved receiver model…
System and method for simulating channels
Granted: March 27, 2018
Patent Number:
9928318
The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code.…
Dynamic flip-flop and multiplexer for sub-rate clock data serializer
Granted: March 20, 2018
Patent Number:
9924466
Methods and systems provide a multiplexing cell and a multiplexing cell system for data serialization. The multiplexing cell may be dynamic D-type flip flop having a single phase clock signal (CLK) and a select input (SEL). An input to the multiplexing cell may be passed to an output if CLK is high and SEL are both high. Otherwise, the output of each multiplexing cell may be in a high impedance state. A multiplexing cell system may include one or more of the multiplexing cells and be…
Security data path verification
Granted: March 20, 2018
Patent Number:
9922209
A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path…
Timing-modulated side channel
Granted: March 13, 2018
Patent Number:
9917655
Physical-layer information is conveyed within a packetized communication network via a timing-modulated side channel to yield low-latency physical interface control without consuming host-layer signaling bandwidth. Multi-modal transceivers at opposite ends of a signaling link optionally communicate to confirm mutual support and signaling headroom for timing-modulated information exchange before transitioning from an in-band feedback mode to a side-channel feedback mode.
Method and system for efficiently determining differential voltages for electrostatic discharge simulations
Granted: March 13, 2018
Patent Number:
9916403
An improved approach is provided for determining differential voltages for driver and receiver pairs as a result of electrostatic discharge (ESD) events including identifying circuits of interest, re-characterizing the circuits of interest into a system for evaluating differential voltages, determining the differential voltages for ESD pin locations, and outputting results after iterating through all the ESD pin locations. In some embodiments, re-characterizing may include performing a…
Multiphase I/O for processor-based emulation system
Granted: March 6, 2018
Patent Number:
9910810
Systems and methods of emulating application-specific integrated circuits using multiple execution phases, where different inputs and outputs are used or produced by components of the emulation system are disclosed. For example, an OMUX may select and transmit different data over a serial bus based on the execution phase of the emulator system. In another example, a processor or cluster may capture outputted data during a first execution phase, execute instructions for a second execution…
Methods, systems, and articles of manufacture for implementing an electronic design with solid-fluid analysis driven techniques
Granted: March 6, 2018
Patent Number:
9910947
The described techniques implement electronic designs with thermal analyses of the electronic design and its surrounding medium by performing thermal modeling that determines at least a thermal RC network for an electronic design. These techniques further generate a thermal network for the electronic design and one or more surrounding media of the electronic design and generate or modify the electronic design with an implementation process at least by guiding the implementation process…
