Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization
Granted: October 18, 2016
Patent Number:
9470754
Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide…
Systems and methods for testing integrated circuit designs
Granted: October 11, 2016
Patent Number:
9465896
A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan…
System, method, and computer program product for input/output buffer modeling
Granted: October 4, 2016
Patent Number:
9460250
The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more…
Methods, systems, and computer program product for an integrated circuit package design estimator
Granted: September 27, 2016
Patent Number:
9454634
Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and…
Differential signal detector and full wave rectifier circuit thereof with common mode signal rejection
Granted: September 20, 2016
Patent Number:
9450511
A full wave rectifier (270) for use as part a differential signal detector (400) detects both high and low envelopes of differential signals (RXa, RXb) at a pair of differential inputs (202, 204) and provides a sense signal (VSENSE) at an output (220) thereof. The differential signal detector (400) includes both the full wave rectifier (270) and a voltage reference source (260) having a circuit architecture in common, and a comparator for comparing the sense signal (VSENSE) with a…
Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs
Granted: September 20, 2016
Patent Number:
9449130
Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second…
System and method for allocating data in memory array having regions of varying storage reliability
Granted: September 20, 2016
Patent Number:
9448883
A system and method are provided for efficient allocation of data in a memory array having regions of varying storage reliability. Storage locations for bands of data are selectively allocated in a manner which evenly distributes the probability of error in the data when stored in the memory array in spite of the varying storage reliability. A distribution controller is provided to effect such distribution of data to maintain a collective error rate of each data band within a preselected…
Automatic register port selection in extensible processor architecture
Granted: September 20, 2016
Patent Number:
9448801
This document discusses, among other things, systems and methods to access n consecutive entries of a register file in a single operation using a register file entry index consisting of B bits, wherein B is less than the binary logarithm of a depth of the register file, which corresponds to the number of entries in the register file, and to automatically select, for a set of register arguments for the n consecutive entries, between a register port for each argument requiring a register…
System and method for bit-wise selective masking of scan vectors for -value tolerant built-in self test
Granted: September 20, 2016
Patent Number:
9448282
A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan…
Simplified device model extension using subcircuits
Granted: August 9, 2016
Patent Number:
9411918
A system, method, and computer program product for extending device model parameter specification flexibility when using a subcircuit wrapper. Embodiments facilitate device modeling by allowing a modeling engineer to eliminate the explicit specification of a large set of wrapped device instance parameters as parameters to the subcircuit wrapper itself. A circuit designer may now use the subcircuit wrapper to specify an instance of the subcircuit without having to explicitly provide…
Clock topology planning for reduced power consumption
Granted: August 9, 2016
Patent Number:
9411912
In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable…
High performance static timing analysis system and method for input/output interfaces
Granted: August 2, 2016
Patent Number:
9405882
A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the…
System and method of fast phase aligned local generation of clocks on multiple FPGA system
Granted: August 2, 2016
Patent Number:
9405877
An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based…
System and method for synchronously adjusted delay and distortion mitigated recovery of signals
Granted: August 2, 2016
Patent Number:
9405314
A system and method are provided which incrementally samples and delays a signal passed through a transmission channel thereto. A receiver section is provided with a delay stage including a sample storage portion having a plurality of capacitors. A switch portion selectively switches the capacitors to respectively store incremental samples of the signal received through the channel. A clock source is provided to generate a plurality of periodic clock signals progressively shifted by a…
Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies
Granted: August 2, 2016
Patent Number:
9404969
SOC and other chip designs increasingly feature IP cores, and many copies of the same core may be present in a single chip. Using wrapped cores, it is possible to determine which cores are defective on a chip during test. Multiple instances of identical cores may be tested in parallel to easily determine which cores are failing. The cores compare a signature generated during test of the core against an expected signature, having a pass/fail bit as a result. The pass/fail bits may be…
Virtual verification machine for a hardware based verification platform
Granted: July 26, 2016
Patent Number:
9400858
Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access…
Method and system of collective failure diagnosis for multiple electronic circuits
Granted: July 26, 2016
Patent Number:
9400311
In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the…
Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designs
Granted: July 19, 2016
Patent Number:
9396301
Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy…
View data sharing for efficient multi-mode multi-corner timing analysis
Granted: July 5, 2016
Patent Number:
9384310
A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.
Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques
Granted: July 5, 2016
Patent Number:
9384317
One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s),…
