Using data pattern tracking to debug datapath failures
Granted: June 28, 2016
Patent Number:
9379958
A method and system are provided for profiling data packets as they flow along a datapath in a device under test to locate and debug problems with the datapath or the individual nodes constituting the datapath to thereby expedite formal verification of a device under test and resolve any problems found.
System and method of encoding in a serializer/deserializer
Granted: June 28, 2016
Patent Number:
9379846
In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error…
System and method for identifying constraint solver calls
Granted: June 21, 2016
Patent Number:
9373077
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design. The method may also include associating, using the at least one computing device, an identifier with each constraint solver call utilized in a simulation of the electronic design. The method may also include generating, using the at least one computing device, an application programming interface…
Method, system, and computer program product for implementing repetitive track patterns for electronic circuit designs
Granted: June 21, 2016
Patent Number:
9372955
Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track…
Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques
Granted: June 21, 2016
Patent Number:
9372952
One aspect identifies an interconnect and associated design rule(s) and moves a portion of the interconnect to an adjacent track by using a spreading process on a one-dimensional design data based on the design rule(s) to determine whether the interconnect including the moved portion provides a DRC clean implementation. This aspect examines an interconnect in its entirety without being confined within a prescribed boundary of a fixed region in the layout. The one-dimensional design data…
Guided exploration of circuit design states
Granted: June 21, 2016
Patent Number:
9372949
A model checking tool, which is used to test a circuit design, attempts to reach a target state from an initial state in the state-space of the circuit design using one or more intermediate states. Through an iterative process, the tool identifies intermediate states in the state-space of the circuit design that are used to generate starting states for subsequent iterations of the process. The intermediate states help to restrict the scope of the state-space search to reduce the time and…
Compacting trace data generated by emulation processors during emulation of a circuit design
Granted: June 21, 2016
Patent Number:
9372947
The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further…
Method and apparatus for synchronizing circuits in an emulation system utilizing its serial interconnect network
Granted: June 14, 2016
Patent Number:
9367656
Clock distribution schemes in emulation systems are typically complex and use significant resources. The present disclosure is generally directed to clock distribution to emulation chips using a serial interconnect mesh. A clock distribution tree is overlayed on the emulation chips allocated to a user's circuit design, the tree branching from a root emulation chip using selected serial interconnections and covering each allocated emulation chip. The emulation chips can recover a clock…
Methods, systems, and articles of manufacture for using multiple modes during execution of a program
Granted: June 14, 2016
Patent Number:
9367423
Disclosed are various embodiments relating to methods, systems, and articles of manufacture for using multiple modes during execution of a program. Various embodiments enable a use to switch among multiple modes of execution of a program during an execution of the program without recompiling a higher level code of the program or without restarting the execution of the program from the beginning. Some embodiments enable the user to switch among different modes regardless of whether or not…
Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics
Granted: June 7, 2016
Patent Number:
9361415
Various embodiments implement multi-fabric designs by using respective EDA tools associated with multiple design fabrics to access their respective native design data. Each EDA tool has access to and processes or manipulates its corresponding native design data; and no EDA tools have the visibility of the entire multi-fabric electronic design. Requests for actions are automatically transmitted among these EDA tools to instantiate desired EDA tools and to descend or ascend the…
Hybrid analog/digital clock recovery system
Granted: May 31, 2016
Patent Number:
9356767
In a clock recovery system, a phase detector detects a phase error in an incoming data signal, which it outputs as a differential pair of voltage signals representing positive and negative errors, respectively. A proportional filter generates a proportional offset from the phase error, also as a differential pair of voltage signals. An integral filter generates an integral offset from the proportional offset, using positive and negative voltage controlled oscillators to generate…
Method and system for component parameter management
Granted: May 31, 2016
Patent Number:
9355130
Electronic Design Automation software displays parameters of a component in a graphical user interface. According to an embodiment, parameters of a component may be filtered through the use of a query. A Component Parameter Manager may search through parameter fields in a CDF file for components that match the query and emphasize the matching parameters in a graphical user interface. The parameter fields in a CDF file may also be augmented by a separate file to add search instructions or…
Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabrics
Granted: May 24, 2016
Patent Number:
9348960
Described are methods and systems for netlisting or probing multi-fabric designs that identify a request for process at least a portion of a multi-fabric electronic design and determine a first partial listing of one or more first circuit components in response to the request by at least identifying first design data in a first design fabric of the one or more first circuit components using a first session of a first electronic design automation (EDA) tool. The methods and systems…
Method and system for coverage determination
Granted: May 24, 2016
Patent Number:
9348733
A method, system and non-transitory computer readable storage medium for coverage determination of DUT tests. The method may include obtaining via an input device a selection of a subset of interest of coverage reports included in one or a plurality of saved merged coverage reports. The method may further include using a processing unit, finding a saved merged coverage report of said one or a plurality of saved merged coverage reports that has the smallest number of unwanted coverage…
Method and system to perform performance checks
Granted: May 17, 2016
Patent Number:
9342638
An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two…
Method and system for automatically establishing a component description format (CDF) debugging environment
Granted: May 10, 2016
Patent Number:
9336123
A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow. A user interface is provided for interfacing with a user by displaying a list of debuggable parameters, accepting a selection thereof from a user, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback…
Accurate floating-point calculation method and device
Granted: May 10, 2016
Patent Number:
9335967
A method is provided to narrow down the exponent range throughout most part of the division and square root calculations, to make both software assistance and precision extension unnecessary. The method adjusts the exponent at the end of the calculation to reach IEEE-754 results.
Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness
Granted: May 3, 2016
Patent Number:
9330222
Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the…
System and method for providing an inter-application overlay to communicate information between users and tools in the EDA design flow
Granted: April 5, 2016
Patent Number:
9304981
A method and system are provided for utilizing inter-application image overlays or virtual transparent overlays (VTOs) to communicate information between users and tools along the EDA tool chain in an EDA design flow. VTOs remain divorced from an underlying design file and are able to be manipulated by a plurality of different users in a plurality of different EDA applications or tools, all meant to operate in different stages of the design flow and perform different functions along the…
System and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor
Granted: April 5, 2016
Patent Number:
9305133
A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The…
