Method and system for implementing translations of parameterized cells
Granted: March 29, 2016
Patent Number:
9298871
Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.
Method and system for modeling a flip-flop of a user design
Granted: March 29, 2016
Patent Number:
9298866
The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to…
Method and apparatus for fast low skew phase generation for multiplexing signals on a multi-FPGA prototyping system
Granted: March 22, 2016
Patent Number:
9294094
An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the…
Method and system for dynamic selection of a memory read port
Granted: March 22, 2016
Patent Number:
9292640
A method and system of dynamically selecting a memory read port are provided. In one form a method may comprises, in part, processing instructions in the emulation processors of a hardware functional verification system, storing output bits generated by the LUT in a plurality of storage elements, selecting between a plurality of previously-stored LUT output bits and the output port of the data memory, selecting one of the plurality of output bits stored in the storage elements, and…
Method and system for providing additional look-up tables
Granted: March 22, 2016
Patent Number:
9292639
A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits…
System and method for modifying a data set of a photomask
Granted: March 22, 2016
Patent Number:
9292627
The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation
Granted: March 15, 2016
Patent Number:
9286420
Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs…
Techniques for protecting digital multimedia interfaces
Granted: March 15, 2016
Patent Number:
9288065
A sink circuit for protecting connectivity of a digital multimedia interface, the sink circuit is connected in a sink multimedia device. The sink circuit comprises a sink port configured to provide a connection to a source multimedia device; a termination coupled to the sink port; and a protection component coupled in series between the termination and a power source of the sink multimedia device, the protection component blocks any direct current path through the sink port when the sink…
Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness
Granted: March 15, 2016
Patent Number:
9286432
Disclosed are methods, systems, and articles of manufactures for implementing correct-by-construction physical designs with multiple-patterning-awareness by identifying a first set of grids for a layer based at least in part upon characteristics of other layer(s), identifying a set of tracks for the layer to implement the physical design for the layer, and implementing a shape in the physical design by at least terminating an end of the shape at a grid of the identified first set of…
Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs
Granted: March 15, 2016
Patent Number:
9286421
Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second…
Time to digital converter with successive approximation architecture
Granted: March 15, 2016
Patent Number:
9285778
A time to digital converter with a successive approximation architecture (300) and a method thereof is provided. The time to digital converter (300) includes successive approximation analog to digital converter circuitry (310) configured for converting the differential voltage established in the digital to analog converter (305) of the successive approximation analog to digital converter circuitry (310) to a digital representation thereof, where the differential voltage corresponds to a…
GUI based verification at multiple abstraction levels
Granted: March 8, 2016
Patent Number:
9280627
A system and method that implement an object-oriented model for requirements of a hardware design in order to verify the design. The object-oriented model abstractly captures the design topology, capability, control, and status of the design. An object-oriented model or definition of a hardware design is based on one or more specifications or standards implemented with the design. With the object-oriented model, a system and method for storing and displaying data captured during a test…
Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics
Granted: March 8, 2016
Patent Number:
9280621
Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the…
Methods, systems, and apparatus for clock topology planning with reduced power consumption
Granted: March 8, 2016
Patent Number:
9280614
In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable…
Method and system for re-ordering bits in a memory system
Granted: March 8, 2016
Patent Number:
9280454
A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory…
Method and system for implementing pipeline flip-flops
Granted: February 16, 2016
Patent Number:
9262359
Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.
Simulation observability and control of all hardware and software components of a virtual platform model of an electronics system
Granted: February 16, 2016
Patent Number:
9262305
Aspects of the present invention describe a system and method for a user of an event-driven simulation environment and/or embedded software debugger interface to step through the source code of components modeled by the environment/debugger, including the embedded software or hardware model source code. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, the source code of each modeled component may be…
Simulation observability and control of all hardware and software components of a virtual platform model of an electronics system
Granted: February 16, 2016
Patent Number:
9262299
Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify complex breakpoint conditions and actions which allow both hardware and software states to be accessed. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, a global identifier may be used to unambiguously identify each element, object, and subcomponent of the modeled system. The unambiguous global…
Method and system for automatic generation of solutions for circuit design rule violations
Granted: February 9, 2016
Patent Number:
9256708
Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to…
Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs
Granted: February 2, 2016
Patent Number:
9251299
One aspect creates or identifies a rule, identifies or creates track pattern(s), and associate the rule with the track pattern(s). The rule is used to guide physical implementation tools to implement electronic designs which not only satisfy the constraints of the rule but also the constraints of the track pattern(s). Some other aspects are directed at interpretation or automatic association or assignment of a layer constraint by determining whether a track pattern on a layer with a…
