Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network
Granted: February 2, 2016
Patent Number:
9250900
Methods and systems for implementing a microprocessor with a selective register file bypass network are disclosed. Late bypasses are removed from a register file bypass network of a microprocessor design. One or more late bypasses are then added back to the register file bypass network based at least in part upon the results of analyzing a plurality of instructions that are to be processed in an instruction pipeline of the microprocessor. An electronic design for at least the register…
System and method for data mining safe operating area violations
Granted: January 26, 2016
Patent Number:
9245088
A system and method for managing SOA assertion violations and related simulator output. Embodiments transform simulator output into descriptive data regarding SOA violations for relational database storage and processing. The database executes queries on the descriptive data according to user input specifying particular descriptive data and SOA assertion violations of interest, and outputs query results for further user action. Individual and accumulative SOA violations are more easily…
Enriched log viewer
Granted: January 26, 2016
Patent Number:
9244814
A computer implemented method of debugging with enriched message log capability may include, for each instance during an execution of a program to be debugged in which a message is issued, automatically analyzing the program code included in a scope of the program relating to the message to identify one or a plurality of variables. The method may also include saving on a non-transitory computer readable storage medium a value at that instance of each of said one or a plurality of…
Method and system for debugging a program that includes declarative code and procedural code
Granted: January 19, 2016
Patent Number:
9239773
A method for debugging a program that includes declarative code and procedural code includes presenting to a user on an output device data relating to execution of the procedural code and data relating to execution of the declarative code. The data is presented in the form of a sequence of execution events corresponding to a computational flow of an execution of the program.
Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
Granted: December 29, 2015
Patent Number:
9223925
Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or…
Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics
Granted: December 29, 2015
Patent Number:
9223915
Disclosed are various techniques that check, verify, or test multi-fabric designs by receiving a request for checking correctness of a multi-fabric design across at least a first design fabric and a second design fabric. A request for action is transmitted from a first EDA tool session to a second EDA tool session. Connectivity information of second design data in the second design fabric is identified by the second EDA tool session in response to the request for action from the first…
Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks
Granted: December 15, 2015
Patent Number:
9213793
One aspect interconnects two regions subject to different rules and using transition rule(s) in a transition region or cost mechanism(s), where these rules may include soft rule(s), hard rule(s), or combinations thereof. These two regions may reside on the same routing layer or on different routing layers. This aspect allows physical design tools to transition across gridded, gridless, tracked, or trackless regions subject to different rules on the same or different layers. Another…
Simulation based system and method for gate oxide reliability enhancement
Granted: December 15, 2015
Patent Number:
9213787
A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output…
Automated adjustment of wire connections in computer-assisted design of circuits
Granted: December 8, 2015
Patent Number:
9208277
In one aspect, a method for providing a circuit design includes defining an interconnect network comprising a plurality of wire connections, the defining performed after modification of the interconnect network and before completion of the interconnect network. An adjustment technique is applied to the wire connections of the defined interconnect network before completion of the interconnect network.
Enabling IP execution on a simulation execution platform
Granted: December 8, 2015
Patent Number:
9208282
In a system and method that simulates a design including a third party IP component, a driver for the IP component is compiled and executed in a workstation implementing the simulation platform for the design. The source code for the driver is modified to allow the simulation to reroute certain functions that would cause the simulator to hang until an event occurs that would unlock the simulation. The rerouting includes storing instruction location, state information, and any other…
Methods, systems, and articles of manufacture for implementing clone design components in an electronic design
Granted: December 8, 2015
Patent Number:
9208273
Various embodiments implement electronic designs with cloning techniques by identifying a root device corresponding to a master design in an electronic design, performing one or more sets of searches for device correspondence with respect to the root device, and implementing the electronic design by at least characterizing the device correspondence based at least in part upon one or more criterion for the one or more sets of searches. These techniques implement the electronic design by…
Transaction correlation system
Granted: December 8, 2015
Patent Number:
9208271
Embodiments provide methods, systems, and devices involving transaction correlation tools that may record a limited number of run attributes yet are likely to be important in the debugging process. Some embodiments may include novel tabular representations of the runs. Embodiments may allow the user to specify directives for the recording of the runs and the creation of these tables. Embodiments may include comparing sets of failing and passing runs, which may be generated at random.…
Method to preview an undo/redo list
Granted: December 8, 2015
Patent Number:
9208137
A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document.
System and method for dust contamination prevention and removal in fiber-optic panel-mount assemblies
Granted: December 8, 2015
Patent Number:
9207454
A system and method for preventing contamination of an array of fiber optic connectors. The system includes a housing for retaining the array of fiber optic connectors in an adjacent relation and an arrangement for delivering pressurized gas into said housing to prevent external contamination entering said housing and causing debris on a surface of one or more of the connectors. A control arrangement is provided for deactivating air flow after all optical connections are covered and…
Integrated circuit floorplan having feedthrough buffers
Granted: December 1, 2015
Patent Number:
9201999
A method and a system are provided for planning feedthrough ports on a floorplan for an integrated circuit. In one example, the system groups paths (e.g., nets) into mutually exclusive families of paths (e.g., nets). The system analyzes the simpler path combinations for each path family. Advantageously, the system can find consistent design solutions for paths (e.g., nets), while adding fewer ports and fewer nets, within a practical amount of time.
System and method for lateral connection between interface devices with bypass of external network
Granted: December 1, 2015
Patent Number:
9203895
A system and method are provided for offloaded lateral transmission between protocol interface devices in an electronic system. Such offloading allows the lateral transmission of data and/or instructions between disparate protocol interface devices without burdening the electronic system's resources, such as the primary processor, memory, and/or system bus. A lateral communication controller is provided to intercouple the first and second protocol interface devices and selectively…
System and method for connecting components in an electronic design
Granted: December 1, 2015
Patent Number:
9202006
The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow…
System, method, and computer program product for ensuring that each simulation in a regression is running a unique configuration
Granted: December 1, 2015
Patent Number:
9202004
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiment may also include calculating, using one or more processors, configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements…
System and method for electronic design routing between terminals
Granted: December 1, 2015
Patent Number:
9202001
The present disclosure relates to a computer-implemented method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle. The method may also include routing the plurality of rats…
Implementing designs of guard ring and fill structures from simple unit cells
Granted: December 1, 2015
Patent Number:
9202000
Systems and methods for creating and placing custom guard rings create a guard ring from a plurality of unit cells reflecting the devices that are enclosed in the guard ring. Using a unit cell identified by a design tool user as the basic unit of the guard ring, with a few additional setup parameters, a complete, content-aware guard ring is created. The guard ring will consist of a collection of the identified unit cells placed around the circuit devices that are to be protected. The…
