Connector and interface circuit for simultaneous content streaming and user data from handheld devices
Granted: November 24, 2015
Patent Number:
9197340
An apparatus for enabling simultaneous multimedia content and user data streaming from a handheld device to a display device is disclosed. The apparatus enables power charging of the handheld device while streaming the multimedia content and the user data from the handheld device. The apparatus comprises a data-multimedia-power interface (DMPI) connector installed in the handheld device and designed to enable the transport of at least high definition multimedia signals, data signals, a…
Apparatus for enabling simultaneous content streaming and power charging of handheld devices
Granted: November 24, 2015
Patent Number:
9197023
An apparatus for enabling simultaneous multimedia content streaming and power charging of handheld devices, comprises a universal connector installed in a first device and enables connectivity of at least one multimedia display interface and at least one data interface with a second device, the first device is connected to the second device using a charging-streaming cable having, at one end, a first connector compliant with the universal connector, and at the other end, a second…
Common shared memory in a verification system
Granted: November 24, 2015
Patent Number:
9195784
The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the…
System, method, and computer program product for constraint solving
Granted: November 17, 2015
Patent Number:
9189743
The present disclosure relates to a computer-implemented method for iteratively solving a constraint satisfaction problem. The method may include assigning a value to each of one or more variables associated with the constraint satisfaction problem, each of the one or more variables having a first domain. The method may also include identifying an invalid solution resulting from a first value assigned to a first variable. The method may further include replacing the first value with a…
System, method, and computer program product for power supply network visualization
Granted: November 17, 2015
Patent Number:
9189578
Embodiments of the present disclosure may include receiving, at one or more computing devices, the electronic circuit design, wherein the electronic circuit design includes at least one Unified Power Format file. Embodiments may further include generating, using the one or more computing devices, a schematic of a power supply network, based upon, at least in part, the at least one Unified Power Format file, the schematic including one or more power supply network components.
Method and apparatus for memory power reduction
Granted: November 17, 2015
Patent Number:
9189050
A method and system for reducing memory power usage are disclosed. The method and system comprise receiving at least one low-priority command and delaying execution of the at least one low-priority command until a predetermined event occurs, wherein the memory remains in a low-power mode until the predetermined event occurs.
Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
Granted: November 10, 2015
Patent Number:
9183343
Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of…
Formalizing IP driver interface
Granted: November 10, 2015
Patent Number:
9183331
A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.
Method and system for navigating hierarchical levels using graphical previews
Granted: November 10, 2015
Patent Number:
9182948
Navigating hierarchical levels of a design using graphical preview images. In one aspect, a method for providing a preview image for a design includes causing a display of a main image depicting a first portion of the design, the design organized into multiple hierarchical levels, each level having a different amount of abstraction of graphical information of the design. A preview image smaller than the main image is displayed, portraying a second portion of the design at a different…
Methods, systems, and articles of manufacture for creating or manipulating electrical data sets for an electronic design
Granted: November 3, 2015
Patent Number:
9177095
Disclosed are method(s), system(s), and article(s) of manufacture for creating or manipulating electrical data sets for an electronic design across multiple abstraction levels. The method identifies simulation result(s) obtained from simulation run(s) for an electronic circuit or at least a portion thereof, identifies at least a part of one or more sets of simulation results, each of which is obtained from a simulation run for the electronic circuit or at least a portion thereof at the…
Routing interconnect of integrated circuit designs with varying grid densities
Granted: November 3, 2015
Patent Number:
9177093
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the…
Formal verification coverage metrics for circuit design properties
Granted: November 3, 2015
Patent Number:
9177089
A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the…
Method and system for reducing redundant logic in an integrated circuit
Granted: October 27, 2015
Patent Number:
9171116
An apparatus and method are provided for removing redundant logic in a logic design of an integrated circuit (IC) design. The apparatus and method optimizes the integrated circuit by selecting stuck-at constant registers in the logic design, propagating a constant output value of the stuck-at constant registers across output nets of the stuck-at constant registers, identifying redundant logic in the logic design based on the propagation of the constant input value across the output net…
Hardware emulation method and system using a port time shift register
Granted: October 27, 2015
Patent Number:
9171111
A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication…
Hierarchical compaction for test pattern power generation
Granted: October 27, 2015
Patent Number:
9170301
A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the…
Method and apparatus for identifying double patterning color-seeding violations
Granted: October 20, 2015
Patent Number:
9165104
A method for automatically performing a double patterning (DP) color-seeding check in order to discover color-seeding violations in an IC design layout. The method of some embodiments receives a layer of the IC design layout and performs an analysis on the layer of the design layout to determine several error paths. Each error path connects two color-seeding shapes that have a color-seeding violation. For each pair of shapes that has a color-seeding violation, the method of some…
Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs
Granted: October 20, 2015
Patent Number:
9165103
Various aspects described herein create tessellated regions by identifying tessellation lines in one or more directions based at least on fixed shape(s) or route(s). New cells or shapes are added to the design by aligning at least some of the boundary segments of the new cells or shapes with existing tessellation lines. Tessellation lines are dynamically adjustable. At least some tessellated regions are associated with initial or tentative track pattern labels some of which are…
Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs
Granted: October 20, 2015
Patent Number:
9165098
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path…
Method and system for implementing a stream reader for EDA tools
Granted: October 20, 2015
Patent Number:
9164969
Disclosed is a method, system, and computer program product for implementing efficient access to stream data. The present approach implements a stream reader that supports either reading the entire layout (e.g., loading the contents of the user-specified top cell and all its progeny) into memory, or just a portion of it (e.g., loading only the contents of the user-specified top cell and its progeny that overlapped a user-specified bounding box). Some approaches provide a mechanism to…
Formal verification coverage metrics of covered events for circuit design properties
Granted: October 13, 2015
Patent Number:
9158874
A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the…
