Robust erase page detection logic for NAND flash memory devices
Granted: October 13, 2015
Patent Number:
9159423
The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target…
Formal verification coverage metrics of covered events for circuit design properties
Granted: October 13, 2015
Patent Number:
9158874
A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the…
Multi-phase models for timing closure of integrated circuit designs
Granted: October 6, 2015
Patent Number:
9152742
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing…
Generating modular and hierarchical execution code from untimed and timed block diagrams
Granted: October 6, 2015
Patent Number:
9152390
The invention is directed to a method, computer program product and apparatus for generating modular, hierarchical code from block diagram notations. The generated code for a block preserves the hierarchical structure of the block, and is independent of where this block is embedded. Therefore, code for a block need to be generated only once, and then stored and reused multiple times, each time the block is reused in a diagram.
System and method for boosting a selective portion of a drive signal for chip-to-chip transmission
Granted: September 29, 2015
Patent Number:
9148130
A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting…
System and method to drag instance master physical shell
Granted: September 22, 2015
Patent Number:
9141746
A system and method for enabling the display and movement of a boundary box of an instance master inclusive of specific predetermined geometric figures, including master pins, master halo and master boundary edges, is provided. The system and method provides for improved utilization of computer resources and enables users of the present invention to be able to drag and use instance master in their designs more efficiently and rapidly.
Methods, systems, and articles of manufacture for providing evolving information in generating a physical design with custom connectivity using force models and design space decomposition
Granted: September 22, 2015
Patent Number:
9141743
Disclosed are methods, systems, and articles of manufactures for providing evolving information in generating a physical design with custom conductivity using force models and design space decomposition by first presenting a layout area in an interface. The interface then displays the evolution of the physical design in the interface to reflect temporal states of the physical design during generation of the physical design after the system receives an input for the physical design and a…
Methods, systems, and articles of manufacture for implementing mixed-signal electronic circuit designs with power data in standardized power formats
Granted: September 22, 2015
Patent Number:
9141741
Some aspects are directed at methods and systems that directly specifies or uses standardized power data in standardized format(s) in various design tasks for implementing mixed-signal electronic designs by using native process(es) or module(s) of standardized power format framework(s) to evaluate legal signals or expressions to generate the first output and evaluation process(es) or module(s) to evaluate illegal signals or expressions to generate the second output for the design tasks,…
Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data
Granted: September 22, 2015
Patent Number:
9141740
Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual…
Home network architecture for delivering high-speed data services
Granted: September 15, 2015
Patent Number:
9137485
A home multimedia network comprises a plurality of source nodes, wherein each of the source nodes includes an apparatus for concurrently transmitting and receiving high-speed data services; a plurality of sink nodes, wherein each of the sink nodes includes the apparatus for concurrently transmitting and receiving high-speed data services; a switch for connecting a first group of the plurality of source nodes located at one room to one or more sink nodes located at a different room than…
Current switching digital-to-analog converter with hybrid current switching circuit having low-memory effect
Granted: September 15, 2015
Patent Number:
9136854
In one embodiment of the invention, a digital to analog convertor (DAC) is disclosed for converting a digital input signal into an analog output signal. The DAC includes a switch controller coupled to a digital input signal; a bias voltage generator coupled to a first terminal of an analog voltage power supply; and a switched current source array coupled to the switch controller and the bias voltage generator. The bias voltage generator generates a bias voltage. The switch controller…
Methods for construction and optimization of a clock tree plan for reduced power consumption
Granted: September 15, 2015
Patent Number:
9135375
In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable…
Method and system for implementing an interface for I/O rings
Granted: September 15, 2015
Patent Number:
9135373
Disclosed are improved methods, systems, and computer program products for implementing an interface for visualizing, generating, and optimizing an I/O ring arrangement for an electronic design. A ribbon-based interface may be employed to visually see and control the design of the I/O ring.
Synchronized three-dimensional display of connected documents
Granted: September 8, 2015
Patent Number:
9129081
A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window.…
Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
Granted: September 8, 2015
Patent Number:
9129078
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net…
Half rate serialization and memory cell for high speed serializer-deserializer
Granted: September 1, 2015
Patent Number:
9124278
Methods and systems provide a memory cell and a memory cell system for data serialization. In an embodiment, a half-rate serialization procedure uses a half-rate differential clock to output full-rate serial data. In an embodiment, the memory cell system includes two memory cells each receiving a respective data stream. Each memory cell may be controlled by a respective clock, the clocks being substantially mutually exclusive such that the output of each memory cell becomes alternately…
Method of using continuous parameter value updates to realize rapid Pcell evaluation
Granted: September 1, 2015
Patent Number:
9122834
A system, method, and computer program product for using continuous parameter value updates to rapidly evaluate parameterized cells in a design tool. Embodiments display parameters and corresponding parameter values of parameterized cells in a circuit design in a GUI, adjust parameter values according to user input, evaluate the parameterized cell, and present results of the evaluating in the GUI during the displaying. Parameters influence circuit layout, circuit schematics, or…
System and method for maintaining dynamic visual cue for associated circuitry of schematic object
Granted: September 1, 2015
Patent Number:
9122384
A method and system are provided for maintaining dynamic visual cues/graphic indicia for associated circuitry of a schematic object. The dynamic visual cues or graphic indicia indicate a number of states of the parent circuit object and its associated circuitry. The visibility, placement status, and other attributes of the parent or associated circuitry may be quickly discerned by inspection of the visual indicia. Navigation, including manipulations of one or both of the parent and…
Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns
Granted: August 25, 2015
Patent Number:
9117052
Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a…
System and method for preventing proper execution of an application program in an unauthorized processor
Granted: August 25, 2015
Patent Number:
9117060
A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling…
