Method, system, and computer program product for implementing firmware-driven, dynamically configurable pulse-density modulation audio intellectual property
Granted: August 18, 2015
Patent Number:
9111047
A programmable intellectual property block includes a PWM processor core to perform audio processing on input audio signals with firmware-driven modules to generate PWM output samples without using digital-analog converters or application processors. PWM processor core directly writes PWM output samples to queues of PWM peripherals to generate and transmit PWM digital pulses used by power stage(s) to drive electroacoustic transducers. Audio processing module(s) and PWM processing…
Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design
Granted: August 11, 2015
Patent Number:
9104830
Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple…
Method and system for automatic generation of processor datapaths
Granted: August 11, 2015
Patent Number:
9104827
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers.…
Methods, systems, and articles of manufacture for implementing physical designs with force directed placement or floorplanning and layout decomposition
Granted: August 4, 2015
Patent Number:
9098667
Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete…
Ranking process for simulation-based functional verification
Granted: August 4, 2015
Patent Number:
9098637
The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in…
Method and system for testing and analyzing user interfaces
Granted: August 4, 2015
Patent Number:
9098635
A system and method is described in which the state of the art in automated software applications is significantly improved. According to some approaches, interface testing is implemented and based upon a verification language and a verification environment. The system and method support the concepts of constrained random test generation, coverage, constrained random generation, and dynamic checks.
Version management mechanism for fluid guard ring PCells
Granted: July 28, 2015
Patent Number:
9092586
A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous…
Method and system for implementing a user interface with ghosting
Granted: July 28, 2015
Patent Number:
9092110
An approach is described for implementing a GUI that an account for illegal operations by the user. Visual ghosting is implemented that includes separation support. If an object is manipulated into an impermissible/unacceptable configuration, ghosting separation is performed to display multiple ghost images, where a first ghost image shows a legal configuration of the object and a second ghost image shows the current configuration of the object. The second ghost continues to track the…
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs
Granted: July 21, 2015
Patent Number:
9087174
Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look…
Method for link resets in a SerDes system
Granted: June 30, 2015
Patent Number:
9071256
The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common…
Contention-free level converting flip-flops for low-swing clocking
Granted: June 30, 2015
Patent Number:
9071238
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop…
System and method for augmenting frequency tuning resolution in L-C oscillation circuit
Granted: June 30, 2015
Patent Number:
9071193
A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at…
System and method implementing full-rate writes for simulation acceleration
Granted: June 30, 2015
Patent Number:
9069918
A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation…
Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints
Granted: June 23, 2015
Patent Number:
9064063
Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take…
Method and apparatus for optimizing access to control registers in an emulation chip
Granted: June 23, 2015
Patent Number:
9063831
The present patent document relates to a method and apparatus for optimizing access to control registers in an emulation chip. Control messages include in one half of the message a write-mask bits for the corresponding control bits in the other half of the word. A single message from the host workstation can be used to update several bits of the register using a single message, rather than reading, modifying, then writing back each bit individually. Only the bits desired to be updated…
Method and mechanism for verifying and simulating power aware mixed-signal electronic designs
Granted: June 16, 2015
Patent Number:
9058440
Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the…
Method and system for implementing an improved interface for designing electronic layouts
Granted: June 9, 2015
Patent Number:
9053289
Disclosed is a method and system for visualizing legal locations of edges and dimensions for an object being placed or edited in the layout. During the design process, visual indicators may be provided to the user to indicate the legal locations at which edges of an object may be placed in the layout. Gravitation and/or snapping may be provided automatically identify and/or move the edges to the legal locations. However, the user can control whether and under what circumstances the…
Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
Granted: June 9, 2015
Patent Number:
9053270
Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet…
Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designs
Granted: June 9, 2015
Patent Number:
9053259
Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analysis on electronic designs. Some embodiments perform squish analysis with a squish pattern library on…
Method and system for performing verification of an electronic design
Granted: June 2, 2015
Patent Number:
9047427
An improved approach for designing and verifying electronic designs at different levels of abstractions is disclosed. An electronic design undergoes high level verification, where the results of the high level verification can be guaranteed to be correct at the RTL level. This can be implemented by ensuring that model consistency rules are followed to generate high level (enhanced transaction level) models and/or RTL data. In this way, properties that are verified at one level of…
