System and method for analog verification IP authoring and storage
Granted: June 2, 2015
Patent Number:
9047424
A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP…
Software modification methods to provide master-slave execution for multi-processing and/or distributed parallel processing
Granted: May 26, 2015
Patent Number:
9043771
In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational…
Methods, systems, and articles of manufacture for implementing physical design using force models with custom connectivity
Granted: May 26, 2015
Patent Number:
9043742
Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first…
Synthesis of fast squarer functional blocks
Granted: May 26, 2015
Patent Number:
9043735
In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least…
Double data rate memory physical interface high speed testing using self checking loopback
Granted: May 26, 2015
Patent Number:
9043662
A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback…
System and method for containing analog verification IP
Granted: May 19, 2015
Patent Number:
9038008
A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits…
Method and system for semiconductor design hierarchy analysis and transformation
Granted: May 19, 2015
Patent Number:
9038002
A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made…
System and method for automated simulator assertion synthesis and digital equivalence checking
Granted: May 12, 2015
Patent Number:
9032347
A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is…
Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators
Granted: May 5, 2015
Patent Number:
9026966
The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a processor-based emulator. A set of linked databases are compiled for the DUT, one for hardware emulation (without timing information for the DUT) and one for software simulation (including timing information) that remain synchronized during runtime. The compiled design is run in a hardware emulator during…
Reverse interface logic model for optimizing physical hierarchy under full chip constraint
Granted: May 5, 2015
Patent Number:
9026978
A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a…
System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
Granted: May 5, 2015
Patent Number:
9026963
An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
Systems and methods for lithography-aware floorplanning
Granted: May 5, 2015
Patent Number:
9026960
The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some…
Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout
Granted: May 5, 2015
Patent Number:
9026958
Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple…
System, method, and computer program product for identifying differences in a EDA design
Granted: April 28, 2015
Patent Number:
9021349
The present disclosure relates to a computer-implemented method for generating an electronic design automation differences report is provided. The method may include modifying instructions configured to generate a report of an electronic design and generating a data file based upon, at least in part, the modified instructions. The method may further include converting the data file to a second data file using, at least in part, the template. The method may also include generating a…
Integrated circuit simulation using analog power domain in analog block mixed signal
Granted: April 28, 2015
Patent Number:
9020797
A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to…
Image-based stimulus for circuit simulation
Granted: April 28, 2015
Patent Number:
9020277
Certain embodiments enable image-based stimulus for circuit simulations by extracting a waveform from an image and using that waveform to simulate a circuit. Image-processing aspects may include edge-detection processes to identify a boundary of the waveform in the image.
Integrated clock gating cell for circuits with double edge triggered flip-flops
Granted: April 28, 2015
Patent Number:
9018995
A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock…
System and method incorporating an arithmetic logic unit for emulation
Granted: April 21, 2015
Patent Number:
9015026
A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs…
System and method for simulator assertion synthesis and digital equivalence checking
Granted: April 14, 2015
Patent Number:
9009635
A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is…
Lumped aggressor model for signal integrity timing analysis
Granted: April 7, 2015
Patent Number:
9003342
A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to…
