Lumped aggressor model for signal integrity timing analysis
Granted: April 7, 2015
Patent Number:
9003342
A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to…
Synthesis of clock gated circuit
Granted: April 7, 2015
Patent Number:
9003339
Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional…
System and method for interleaved analog-to-digital conversion having scalable self-calibration of timing
Granted: April 7, 2015
Patent Number:
9000962
A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock…
Method and system for providing an implicit unknown value to user ENUM data constructs in an HDL system to model power shutoff in simulation
Granted: March 31, 2015
Patent Number:
8997068
A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.
Method and system for debugging of compiled code using an interpreter
Granted: March 31, 2015
Patent Number:
8997049
A system, method, and computer program product is disclosed that for debugging errors in software code. According to some approaches, techniques are provided for performing on-the-fly switching from compiled to interpretive debugging for a software program. The test starts with compiled code, and when it needs to stop for debugging, the debugging occurs in interpretive mode. Once debugging has concluded, the execution can switch back to compiled mode. In this way, the debugging…
System and method for self alignment of pad mask
Granted: March 31, 2015
Patent Number:
8997026
A system and method provide semiconductor fabrication mask creation techniques that align the device features patterned with a first core mask with one or more pad features patterned with a subsequent pad mask. Shapes representing the pad features may be included in the core mask by reducing on all sides, the shape of the pad feature in the core mask by the width of the spacer material. A pad mask then may be created to include a shape of the pad feature that may overlap a portion of the…
System and method for fault sensitivity analysis of digitally-calibrated-circuit designs
Granted: March 31, 2015
Patent Number:
8996348
An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.
Method and apparatus for optimizing memory-built-in-self test
Granted: March 24, 2015
Patent Number:
8990749
Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an…
Method for mutation coverage during formal verification
Granted: March 24, 2015
Patent Number:
8990746
The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit. The method may further include generating one or more faults in a cone of influence of an assertion and placing a constraint configured to model an original design for the one or more faults. The method may also include initiating formal verification on the electronic design while ignoring all…
Method to adaptively calculate resistor mesh in IC designs
Granted: March 17, 2015
Patent Number:
8984468
Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide…
Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design
Granted: March 17, 2015
Patent Number:
8984465
Various aspects described herein identify an area in an electronic design, identify a set of track patterns or track pattern groups for the area based on a set of criteria, and iteratively implement the electronic design in the area using at least some of the set of track patterns. These aspects may dynamically or iteratively update the assignment of one or more track patterns to the region based at least in part upon the implementation of the electronic design in the area or one or more…
Timing budgeting of nested partitions for hierarchical integrated circuit designs
Granted: March 10, 2015
Patent Number:
8977995
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all…
Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints
Granted: March 10, 2015
Patent Number:
8977994
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay…
Methods, systems, and articles of manufacture for dynamic protection of intellectual property in electronic circuit designs
Granted: March 10, 2015
Patent Number:
8977863
Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in…
Dual row I/O with logic embedded between rows
Granted: March 10, 2015
Patent Number:
8975919
The present invention provides for a method and circuit of an integrated circuit (IC) having dual row input/output (I/O). The circuit having a plurality of dual I/Os including an upper row of I/O and a lower row of I/O, with logic arranged in communication between the upper and the lower rows of the dual row I/O. The connectivity with the logic circuits of the present invention therefore provides for improving reliability and performance through more similar and uniform pathway…
Multimode physical layer module for supporting delivery of high-speed data services in home multimedia networks
Granted: March 3, 2015
Patent Number:
8973062
A multimode physical (MMP) layer circuit for physical (PHY) layer handling of signals transported over a high-definition multimedia interface (HDMI) cable in a home multimedia network, wherein the signals are compliant with at least two different PHY layer modes. The MMP layer circuits comprises a plurality of PHY transceivers respectively coupled to a plurality of TP channels of the HDMI cable through a HDMI connector, wherein each PHY transceiver of the plurality of PHY transceivers…
Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
Granted: February 24, 2015
Patent Number:
8966421
In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current…
Finite-state machine encoding during design synthesis
Granted: February 24, 2015
Patent Number:
8966416
Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic…
Metastability error detection and correction system and method for successive approximation analog-to-digital converters
Granted: February 17, 2015
Patent Number:
8957802
A system and method are provided for the detection and correction of metastability errors in a successive approximation analog to digital converter (ADC). The successive approximation ADC (40) includes a comparator unit (424) that includes a NAND gate circuit (550) that outputs a comp_rdy_n signal when the comparator (500) has latched a result. ADC (40) includes a metastability detection and correction circuit (425) that includes a first logic circuit (700) that monitors the comp_rdy_n…
Emulation system with improved reliability of interconnect and a method for programming such interconnect
Granted: February 17, 2015
Patent Number:
8959010
A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate…
