Method and system for performing fast electrical analysis and simulation of an electronic design for power gates
Granted: February 10, 2015
Patent Number:
8954917
A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the…
Device mismatch contribution computation with nonlinear effects
Granted: February 10, 2015
Patent Number:
8954910
A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal…
Fast monte carlo statistical analysis using threshold voltage modeling
Granted: February 10, 2015
Patent Number:
8954908
A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all…
Methods for physical layout estimation
Granted: February 10, 2015
Patent Number:
8954905
In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.
Chained programming language preprocessors for circuit simulation
Granted: February 10, 2015
Patent Number:
8954307
A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes…
Verification of design libraries and databases
Granted: February 3, 2015
Patent Number:
8949203
Method and system for verifying data in a database. In one aspect, verifying data includes receiving an indication of at least one policy, the at least one policy including at least one rule. A verification process is initiated on target data by implementing the at least one policy, where implementing the at least one policy includes instantiating and applying the at least one rule. The at least one rule causes at least one verification check to be performed on the target data.
System, method, and computer program product for verification using X-propagation
Granted: February 3, 2015
Patent Number:
8949754
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
Granted: February 3, 2015
Patent Number:
8949753
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real…
Double patterning coloring with color balancing
Granted: February 3, 2015
Patent Number:
8949747
Some embodiments of the invention provide a method for balancing the assignment of shapes from a portion of an IC design layout to different masks. The method of some embodiments assigns the shapes to a plurality of masks in a manner that a variation between the numbers of shapes assigned to each mask is within a certain threshold. The method of some embodiments performs a separate analysis for shapes which are outside of a threshold distance from any other shapes.
Techniques for achieving complete interoperability between different types of multimedia display interfaces
Granted: February 3, 2015
Patent Number:
8949481
A multimedia interface cable for achieving complete interoperability between different types of multimedia display interfaces. The cable comprises a first multimedia connector including a plurality of contact pins of at least high-speed multimedia signals and control signals; a second multimedia connector including a plurality of contact pins of least high-speed multimedia signals and control signals; a plurality of un-crossing conducting wires for coupling the plurality of contact pins…
Method and system for power delivery network analysis
Granted: February 3, 2015
Patent Number:
8949102
The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are…
System, method, and computer program product for simulating a mixed signal circuit design
Granted: February 3, 2015
Patent Number:
8949100
The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network…
Method and system for steady state simulation and noise analysis of driven oscillators
Granted: February 3, 2015
Patent Number:
8949099
In a circuit simulation tool in a computer system having one or more computer processors and computer-readable storage, a method for characterizing a driven oscillator circuit having an oscillator coupled to a time-varying input signal includes retrieving information provided in a circuit description of the oscillator circuit. The method also includes forming a frequency-domain harmonic balance equation for the oscillator circuit using the retrieved information provided in the circuit…
Model based analog block coverage system
Granted: January 27, 2015
Patent Number:
8943450
A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks…
Method and apparatus of enabling direct memory access into a target system memory modeled in dual abstractions while ensuring coherency
Granted: January 27, 2015
Patent Number:
8943449
The present patent document relates to a method and apparatus for enabling direct memory access into a target memory subsystem of an electronic system modeled in dual abstractions while maintaining coherency. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. Flags associated with memory pages of the memory subsystem are set to…
Method and apparatus for comprehension of common path pessimism during timing model extraction
Granted: January 20, 2015
Patent Number:
8938703
Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs…
System and method for debugging computer program based on execution history
Granted: January 13, 2015
Patent Number:
8935673
A system and method are provided for enhanced navigation along execution time and code space in a debugger to assist a user in remediating errors, streamlining, or reverse engineering a computer program and the source code thereof. Snapshots of system states are recorded, a causality tree of commands is constructed through execution of the program to be debugged, and an intelligent display of system states captured during runtime and indexed or cross-referenced by time are displayed to…
Methods and apparatus for data path cluster optimization
Granted: January 13, 2015
Patent Number:
8935651
In one embodiment of the invention, a method of logic synthesis is disclosed. The method includes generating a plurality of design architecture alternatives for circuit logic of a data path cluster; saving the plurality of design architecture alternatives; and evaluating the plurality of design architecture alternatives in response to design constraints to select a preferred design architecture.
Methods for single pass parallel hierarchical timing closure of integrated circuit designs
Granted: January 13, 2015
Patent Number:
8935642
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path…
Audio digital signal processor
Granted: January 13, 2015
Patent Number:
8935468
A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation…
