Audio digital signal processor
Granted: January 13, 2015
Patent Number:
8935468
A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation…
Method and system for performing software verification
Granted: January 6, 2015
Patent Number:
8930912
Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a tightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from…
Method and system for generating verification information and tests for software
Granted: December 30, 2014
Patent Number:
8924937
Disclosed is a process, system, and computer program product for generating a verification test or verification environment for testing and verifying software or mixed software/hardware. Object code is analyzed to generate and setup test information and environments. The object code is analyzed to identifying information about the software important or relevant for the verification process. Based upon the information generated form the object code, one or more verification environments…
Constructing equivalent waveform models for static timing analysis of integrated circuit designs
Granted: December 30, 2014
Patent Number:
8924905
In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of…
System and method of designing instruction extensions to supplement an existing processor instruction set architecture
Granted: December 30, 2014
Patent Number:
8924898
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor…
Methods, systems, and articles of manufacture for implementing physical design decomposition with custom connectivity
Granted: December 23, 2014
Patent Number:
8918751
Disclosed are methods, systems, and articles of manufactures for implementing physical design decomposition with custom conductivity by identifying custom, incomplete conductivity for an electronic design, partitioning a physical design space multiple non-overlapping cells, and iteratively moving at least some of the nodes of these multiple cells to generate a floorplan or a placement layout until one or more convergence criteria are satisfied while maintaining the custom, incomplete…
Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space
Granted: December 16, 2014
Patent Number:
8914763
Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the…
Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit
Granted: December 16, 2014
Patent Number:
8914689
A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation…
Routing process
Granted: December 9, 2014
Patent Number:
8910105
The present disclosure relates to a method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may also include generating an independent breakout of the plurality of rats from a source end and a target end of the bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a…
Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space
Granted: December 9, 2014
Patent Number:
8910107
Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the…
System and method for automatically reconfiguring chain of abutted devices in electronic circuit design
Granted: December 9, 2014
Patent Number:
8910100
The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with…
Method for debugging unreachable design targets detected by formal verification
Granted: December 9, 2014
Patent Number:
8910099
The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design associated with the integrated circuit. Embodiments may further include splitting one or more nets in a cone of influence of a target associated with the electronic design. For each split net, embodiments may include placing a constraint that re-joins the net. Embodiments may also include…
Parallel analog to digital converter architecture with charge redistribution and method thereof
Granted: December 2, 2014
Patent Number:
8902093
An analog to digital converting system (200) includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADC 1 ADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) (209, 701) therein. The system further includes a sample and hold circuit (220) coupled to the parallel ADCs by a conductive interconnect wiring pattern (203). The sample and…
Methods, systems, and articles of manufacture for synchronizing software verification flows
Granted: December 2, 2014
Patent Number:
8904358
Disclosed are methods, systems, and articles of manufacture for synchronizing a software verification flow of an application under test (AUT) that uses a user interface. Various embodiments of the methods identify generic application programming interface(s) (API(s)), map menu items of the AUT to logical names, and generate generated API(s) based on the generic API(s) and the mapping results. Some embodiments further generate a custom API by using generated API(s) and implement…
Display process
Granted: December 2, 2014
Patent Number:
8904332
The present disclosure relates to a method for visualizing an electronic circuit design. The method may include receiving the electronic circuit design, wherein the electronic circuit design includes at least one timing constraint. The method may also include identifying the at least one timing constraint and displaying, at a graphical user interface associated with the one or more computing devices, the at least one timing constraint and a physical routing associated with the electronic…
System and method for automatically generating coverage constructs and constraint solver distributions
Granted: December 2, 2014
Patent Number:
8904321
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design and associating, using the at least one computing device, one or more identifiers with each constraint solver call utilized in a simulation of the electronic design. The method may further include automatically generating, using the at least one computing device, a coverage model for one of more…
Method and apparatus for low-pin count testing of integrated circuits
Granted: December 2, 2014
Patent Number:
8904256
A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial…
Operation based polling in a memory system
Granted: December 2, 2014
Patent Number:
8904082
Operation based polling in a memory system. A device manager is provided to perform efficient polling by utilizing the effective bandwidth of the memory system, in a controller coupled to a communication end point. The device manager includes a detection module for detecting a type of operation sent to the communication end point. The device manager also includes a storage module for storing a polling interval value based on a time period of the type of operation in a polling counter of…
Coverage-based bug clustering
Granted: December 2, 2014
Patent Number:
8903823
Embodiments provide tools and techniques for clustering failing runs in a design verification environment to aid in determining causes of the failing runs. Embodiments may include determining multiple failing runs of the design verification environment. Multiple partitions of the multiple failing runs may be generated. Each respective partition may partition one or more subsets of the multiple failing runs into one or more non-overlapping clusters of failing runs. The multiple partitions…
System and method for controlling granularity of transaction recording in discrete event simulation
Granted: December 2, 2014
Patent Number:
8903696
A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity…
