Robust design using manufacturability models
Granted: November 25, 2014
Patent Number:
8898617
The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.
System and method for implementing a trace interface
Granted: November 25, 2014
Patent Number:
8898051
A system and method for selectively capturing and storing emulation data results from a hardware emulation system, which reduces the data bandwidth requirement and the unnecessary consumption of the DRAM memory capacity by uninteresting data. According to one embodiment, a system comprises a trace array for storing one or more frames of data; a first set of hardware control bits that enables the trace array to selectively capture non-continuous windows of data within a frame of data; a…
Physical topology-driven logical design flow
Granted: November 25, 2014
Patent Number:
8898039
A design system provides data structures to store parameters of physical structures that can be viewed and modified through a graphical design interface. Certain of the structures of the physical system may be partitioned into a subsystem such that the data describing the subsystem includes physical topology data defining relative locations of the structures in the physical system. The physical topology data is back-annotated into a logical topology, such as in accordance with a…
Methods for designing intergrated circuits with automatically synthesized clock distribution networks
Granted: November 11, 2014
Patent Number:
8887110
In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to…
Method and system for providing efficient on-product clock generation for domains compatible with compression
Granted: November 11, 2014
Patent Number:
8887019
A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal…
Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices
Granted: November 11, 2014
Patent Number:
8886852
A triple-mode connectivity apparatus for enabling interoperability between a multimedia display interface and a data interface. The apparatus comprises a universal connector installed in a first device and structured to enable connectivity between the multimedia display interface and the data interface of a second device, the first device is connected to the second device using a cable having a first connector compliant with the universal connector and a second connecter compliant with…
System and method for expeditious transfer of data from source to destination in error corrected manner
Granted: November 4, 2014
Patent Number:
8880980
A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination…
Techniques for switching between AC-coupled connectivity and DC-coupled connectivity
Granted: November 4, 2014
Patent Number:
8878590
A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports…
System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions
Granted: October 28, 2014
Patent Number:
8875068
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor…
System and method for generating constrained random values associated with an electronic design
Granted: October 28, 2014
Patent Number:
8875069
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using one or more processors, an electronic design having at least one floating point variable associated therewith. The method may further include converting the at least one floating point variable of the electronic design to a fixed point variable to generate a fixed point implementation of the electronic design. The method may also include processing,…
Fault sensitivity analysis-based cell-aware automated test pattern generation flow
Granted: October 28, 2014
Patent Number:
8875077
A system, method, and computer program product for cell-aware fault model generation. Embodiments determine defects of interest for a cell, typically from cell layout and a transistor-level cell netlist. A circuit simulator performs analog fault simulation on the transistor-level netlist to determine detectable defects from the defects of interest, and detection conditions for the detectable defects. The circuit simulator employs fault sensitivity analysis (FSA) for amenable cells for…
Method and system for automated script generation for EDA tools
Granted: October 28, 2014
Patent Number:
8875087
Disclosed is an improved method, system, and computer program product to perform automated generation and/or modification of control scripts for EDA tools. A script generator/modifier mechanism is used to access an optimization database to identify potential content of the control script. This potential content is then analyzed to identify the appropriate content to insert into the control script, to accomplish the intended goal of the user in operating the EDA tool. The script…
Efficient single-run method to determine analog fault coverage versus bridge resistance
Granted: October 14, 2014
Patent Number:
8863050
In a system, method, and computer program product for analyzing faults in a circuit design, variation of analog fault coverage as a function of bridge resistance values is computed in a single simulation run. A simulator stores intermediate circuit states for each fault resistance value, and performs short interval simulations that may re-use intermediate states as initial solution estimates for simulation of the next fault resistance value. Initial fault resistance values are reduced…
System and method for generating and using a structurally aware timing model for representative operation of a circuit design
Granted: October 14, 2014
Patent Number:
8863052
A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level…
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design
Granted: October 14, 2014
Patent Number:
8863048
Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design by identifying rules for a first layer and for second layer(s) adjacent to the first layer, determining one or more sets of grids based on the rules, extending or implementing shapes to terminate at some grids of the one or more sets of grids, and populating the data of the ends of the shapes in the first layer in a…
General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software
Granted: October 14, 2014
Patent Number:
8862439
In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a…
Methods, systems, and apparatus for reliability synthesis
Granted: October 7, 2014
Patent Number:
8856700
In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability…
Automatic clock to enable conversion for FPGA based prototyping systems
Granted: September 30, 2014
Patent Number:
8850381
The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other…
Method and system for aligning transaction split boundaries to memory burst boundaries
Granted: September 30, 2014
Patent Number:
8850134
A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points,…
Data mining through property checks based upon string pattern determinations
Granted: September 16, 2014
Patent Number:
8838559
A method is provided to evaluate user interaction with a computer user interface (UI) comprising: receiving a property definition that identifies at least one relationship among prescribed string patterns that correspond to one or more UI events; receiving a log file in a computer readable storage device that includes a plurality of respective chunks of information; determining whether the respective chunks of information within the log file includes a respective string pattern that…
