Method and apparatus for derived layers visualization and debugging
Granted: September 16, 2014
Patent Number:
8839183
A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step…
Data mining through property checks based upon string pattern determinations
Granted: September 16, 2014
Patent Number:
8838559
A method is provided to evaluate user interaction with a computer user interface (UI) comprising: receiving a property definition that identifies at least one relationship among prescribed string patterns that correspond to one or more UI events; receiving a log file in a computer readable storage device that includes a plurality of respective chunks of information; determining whether the respective chunks of information within the log file includes a respective string pattern that…
Topology design using squish patterns
Granted: September 9, 2014
Patent Number:
8832621
A system and method for evaluating a design layout by identifying squish patterns for configurations of shapes in windows defined for anchors in the layout, identifying deltas between edges of elements in the windows and reducing each delta to a single width are described. Identified squish patterns may be compared to known patterns to determine if the squish pattern is a known good or bad pattern. A squish pattern may be represented by a pixel map such that each pixel is a reduced delta…
Netlisting analog/mixed-signal schematics to VAMS
Granted: September 9, 2014
Patent Number:
8832612
A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds…
Graphical user interface for physically aware clock tree planning
Granted: September 2, 2014
Patent Number:
8826211
In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster,…
Emulation of power shutoff behavior for integrated circuits
Granted: August 19, 2014
Patent Number:
8812286
A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or…
Computing device mismatch variation contributions
Granted: August 19, 2014
Patent Number:
8813009
A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the…
Accelerated characterization of circuits for within-die process variations
Granted: August 19, 2014
Patent Number:
8813006
In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more…
Analog fault visualization system and method for circuit designs
Granted: August 19, 2014
Patent Number:
8813004
An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.
System and method for transfer of data between memory with dynamic error recovery
Granted: August 19, 2014
Patent Number:
8812898
A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to…
System and method for level shifting signals with adjustably controlled frequency response
Granted: August 19, 2014
Patent Number:
8810301
A system and method are provided for level shifting signals generated by an electronic circuit with selectively controlled frequency response. A first circuit portion defines a primary path for a signal within an upper region of a predefined signal frequency range, and includes a first capacitor unit establishing a voltage level shift for a signal passing therethrough. A second circuit portion selectively defines a secondary path bypassing the primary path for a signal within a lower…
System and method for automated real-time design checking
Granted: August 19, 2014
Patent Number:
8807948
Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the…
Method and apparatus for managing workflow failures by retrying child and parent elements
Granted: August 12, 2014
Patent Number:
8806490
Method of managing workflow failures in a distributed computing environment. A retry value is associated with one or more workflow elements. An element or section of a workflow that does not successfully execute in the distributed computing network is identified. The workflow that does not successfully execute is retried according to a first retry value. The maximum number of times that the first element can be retried is indicated or represented by the first retry value. If one or more…
Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design
Granted: August 12, 2014
Patent Number:
8806405
A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent…
Method and system performing circuit design predictions
Granted: August 12, 2014
Patent Number:
8806396
Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).
Low overhead read disturbance protection method for NAND flash device
Granted: August 12, 2014
Patent Number:
8804418
The present invention provides for a solution benefiting from providing for a method and system to reduce the impact of read disturbance while providing improved system performance through optimized activities with minimal impact to overhead. The present invention provides for a highly effective early page migration mechanism, prior to a manufacturer's endurance limit and without a forced block migration, to reduce read disturbance associated with traditional NAND-based memory…
Methods, systems, and articles of manufacture for synchronizing software verification flows
Granted: August 5, 2014
Patent Number:
8799867
Disclosed are methods, systems, and articles of manufacture for synchronizing a software verification flow of an application that uses a user interface. Various embodiments comprise implementing a menu item as a widget and identifying an operation associated with the menu item. A synchronizer is further identified or created for the operation and then registered with the operation such that the synchronizer is activated when the operation is invoked during the software verification flow.…
Branch and bound techniques for computation of critical timing conditions
Granted: August 5, 2014
Patent Number:
8799840
In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a hierarchy of a netlist of a circuit to determine primary inputs and primary outputs of the circuit at an upper level, and internal vertices of the circuit at lower levels between the primary inputs and the primary outputs; forming a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the primary inputs, the internal…
Method and apparatus of maintaining coherency in the memory subsystem of an electronic system modeled in dual abstractions
Granted: July 29, 2014
Patent Number:
8793628
The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize…
Method and apparatus for efficiently processing an integrated circuit layout
Granted: July 22, 2014
Patent Number:
8789005
A method for efficiently processing a design layout is described. In some embodiments, the method receives an original design layout and a modified design layout. The method identifies a change from the original design layout to the modified design layout by comparing the original and modified design layouts. The method of some embodiments then defines a region based on the location of the identified change within the modified design layout. The method performs a design operation (e.g.,…
