Method and apparatus for efficiently processing an integrated circuit layout
Granted: July 22, 2014
Patent Number:
8789005
A method for efficiently processing a design layout is described. In some embodiments, the method receives an original design layout and a modified design layout. The method identifies a change from the original design layout to the modified design layout by comparing the original and modified design layouts. The method of some embodiments then defines a region based on the location of the identified change within the modified design layout. The method performs a design operation (e.g.,…
System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design
Granted: July 22, 2014
Patent Number:
8788995
A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation…
Physically aware logic synthesis of integrated circuit designs
Granted: July 15, 2014
Patent Number:
8782591
In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives…
Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning
Granted: July 15, 2014
Patent Number:
8782586
Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.
Waveform based variational static timing analysis
Granted: July 15, 2014
Patent Number:
8782583
A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various…
Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
Granted: July 15, 2014
Patent Number:
8782577
Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ…
Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques
Granted: July 15, 2014
Patent Number:
8782570
Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or…
Method and system for implementing parallel execution in a computing system and in a circuit simulator
Granted: July 8, 2014
Patent Number:
8775149
A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and…
Layout fixing guideline system for double patterning odd cycle violations
Granted: July 8, 2014
Patent Number:
8775983
Some embodiments of the invention provide a method for identifying and displaying odd loops and hints for resolution of the odd loops in an IC design layout for printing on multiple masks. The method of some embodiments identifies the hints by evaluating the effectiveness and feasibility of different potential resolutions, ensuring that hints do not create additional odd loops. The method of some embodiments also displays indications of the odd loops and the hints which a user can use to…
Method and system for providing an implicit unknown value to user enum data constructs in an HDL system to model power shutoff in simulation
Granted: July 8, 2014
Patent Number:
8775150
A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.
Fast pattern matching
Granted: July 1, 2014
Patent Number:
8769474
Disclosed are methods, systems, and articles of manufacture for using pattern matching with an integrated circuit layout including recognizing shapes within the IC layout, identifying features for the shapes, and extracting situations for the respective features. The method may further include simulating the situations to determine a set of situations for modification based on an OPC requirement, modifying the set of situations to improve satisfaction of the OPC requirement, and…
Method and system for utilizing hard and preferred rules for C-routing of electronic designs
Granted: July 1, 2014
Patent Number:
8769467
An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.
Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation
Granted: July 1, 2014
Patent Number:
8769456
Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs…
Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
Granted: July 1, 2014
Patent Number:
8769455
Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet…
Register-transfer level (RTL) design checking for exploring simulation and/or synthesis mismatches and ambiguous language semantics using categorization
Granted: July 1, 2014
Patent Number:
8769454
The present disclosure teaches a system and method for register-transfer level (RTL) design checking for exploring mismatches and ambiguous language semantics that occur during the simulation and synthesis phases of the circuit design. In particular, the present disclosure utilizes identified patterns of design violations that occur as a result of these mismatches to create rule objects. The rule objects are then used to identify circuit design violations relating to mismatches between…
Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
Granted: July 1, 2014
Patent Number:
8769453
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet…
Multiple samples with delay in oversampling in phase
Granted: June 24, 2014
Patent Number:
8760210
A method and system in accordance with the present invention provides for a method and circuit for oversampling using a delay element in which input clock signals and input data signals are affected by phase and time delays to provide for the circuit generating samples providing a greater granularity of detail over a period, thereby reducing error probabilities.
Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation
Granted: June 24, 2014
Patent Number:
8762906
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more…
Method and system for implementing circuit simulators
Granted: June 24, 2014
Patent Number:
8762123
A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation…
Methods for synchronized transient-envelope and event-driven simulation of electronic circuits
Granted: June 24, 2014
Patent Number:
8762122
In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient…
