Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness
Granted: June 24, 2014
Patent Number:
8762914
Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the…
Static timing analysis with design-specific on chip variation de-rating factors
Granted: June 24, 2014
Patent Number:
8762908
In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using…
System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design
Granted: June 3, 2014
Patent Number:
8745561
A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to…
Methods for generating a user interface for timing budget analysis of integrated circuit designs
Granted: June 3, 2014
Patent Number:
8745560
In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically…
Emulation system for verifying a network device
Granted: June 3, 2014
Patent Number:
8743735
Various embodiments of the present invention are generally directed to a method and system for functionally verifying a network device design programmed into a hardware logic verification system. The method and system encapsulates and de-encapsulates test patterns generated by a tester application into and out of network packets, which are further encapsulated into and de-encapsulated from enclosing data packets for fast and efficient delivery to the network device. Such method and…
Analog-to-digital converter based decision feedback equalization
Granted: May 27, 2014
Patent Number:
8737490
The present disclosure relates to a method for analog-to-digital converter based decision feedback equalization. The method may include providing an integrated circuit including a SerDes circuitry having a transmit circuitry and a receiver circuitry. The method may further include receiving a high-speed data stream at the receiver circuitry and converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter. The method may also…
Method, system, and program product for interactive checking for double pattern lithography violations
Granted: May 27, 2014
Patent Number:
8739095
Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions…
Probe signal compression method and apparatus for hardware based verification platforms
Granted: May 27, 2014
Patent Number:
8739090
The present patent document relates a method and apparatus for compressing probe system data in hardware functional verification systems used to verify user logic designs. Such systems can create large amounts of data every data cycle, which can include many bits that do not toggle from one cycle to the next. Compressing such data is possible by arranging the data in bytes and determining which bytes contain bits that have changed. A status byte may be generated that conveys which bytes…
Method and system for implementing parallel execution in a computing system and in a circuit simulator
Granted: May 27, 2014
Patent Number:
8738348
A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and…
Analog-to-digital converter based decision feedback equalization
Granted: May 27, 2014
Patent Number:
8737491
The present disclosure relates to a method for Analog-to-Digital Converter Based Decision Feedback Equalization. The method may include providing an integrated circuit including a SERDES circuitry having a transmit circuitry and a receiver circuitry and receiving a high-speed data stream at the receiver circuitry. The method may also include converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter and providing the digital…
Logical design flow with structural compatability verification
Granted: May 20, 2014
Patent Number:
8732651
A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be…
Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects
Granted: May 20, 2014
Patent Number:
8732640
Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different…
Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation
Granted: May 20, 2014
Patent Number:
8732636
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more…
Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test
Granted: May 20, 2014
Patent Number:
8732632
SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested…
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
Granted: May 20, 2014
Patent Number:
8732630
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real…
System, method, and computer program product for hierarchical browsing
Granted: May 13, 2014
Patent Number:
8726224
The present disclosure relates to a computer-implemented method for electronic design visualization. The method may include providing, using at least one computing device, an electronic design and identifying a plurality of power domains associated with the electronic design. The method may further include associating, using the at least one computing device, at least two of the plurality of power domains with a particular group and displaying one or more of the plurality of power…
Method and system for routing optimally between terminals through intermediate vias in a circuit design
Granted: May 13, 2014
Patent Number:
8726222
A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful…
Generating an equivalent waveform model in static timing analysis
Granted: May 13, 2014
Patent Number:
8726211
A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog…
Adjustable gain amplifier system having cleanly adjustable and stable linearized gain
Granted: May 13, 2014
Patent Number:
8723599
An adjustable gain amplifier system having cleanly adjustable and stable linearized gain is provided for amplifying an input signal. The system generally comprises a main amplifier and a linearized transconductance amplifier coupled thereto, which generates an amplified current signal in response to the input signal according to a variably defined transconductance factor. The linearized transconductance amplifier includes a linearized transconductance portion and a translinear current…
Method and system for implementing clock tree prototyping
Granted: May 6, 2014
Patent Number:
8719743
Disclosed is an improved method, system, and computer program product for implementing flexible models to perform efficient prototyping of clock structures in electronic designs, which allows for very efficient analysis of the electronic designs. Some approaches pertain to usage of the flexible abstraction models that also include clock abstractions to more efficiently perform analysis upon the electronic designs. This allows greater analysis efficiency with regards to timing analysis…
