Dual-pattern coloring technique for mask design
Granted: May 6, 2014
Patent Number:
8719765
A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes…
Generalized constraint collection management method
Granted: May 6, 2014
Patent Number:
8719764
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The…
System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
Granted: May 6, 2014
Patent Number:
8719754
A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values…
Method and system for automatically establishing hierarchical parameterized cell (PCELL) debugging environment
Granted: May 6, 2014
Patent Number:
8719745
A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the…
Method and system for implementing clock tree prototyping
Granted: May 6, 2014
Patent Number:
8719743
Disclosed is an improved method, system, and computer program product for implementing flexible models to perform efficient prototyping of clock structures in electronic designs, which allows for very efficient analysis of the electronic designs. Some approaches pertain to usage of the flexible abstraction models that also include clock abstractions to more efficiently perform analysis upon the electronic designs. This allows greater analysis efficiency with regards to timing analysis…
Method and apparatus for identifying double patterning loop violations
Granted: May 6, 2014
Patent Number:
8719737
Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes…
Scan chain diagnostic using scan stitching
Granted: May 6, 2014
Patent Number:
8719651
An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan…
Shooting Pnoise circuit simulation with full spectrum accuracy
Granted: May 6, 2014
Patent Number:
8719000
An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.
Method of eliminating a lithography operation
Granted: May 6, 2014
Patent Number:
8716135
Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a…
Method and apparatus for efficiently inserting fills in an integrated circuit layout
Granted: April 29, 2014
Patent Number:
8713507
A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method…
System and method for solving connection violations
Granted: April 29, 2014
Patent Number:
8713493
The present invention provides a method for resolving a circuit connection violation that comprises categorizing a circuit chain with the connection violation into a class, and performing one or more transformation algorithms on the circuit chain from the group consisting of a chain mirror, a cascade mirror, a cascade mirror permute, and a cut chain mirror algorithm based on the class of the circuit chain.
Aware manufacturing of integrated circuits
Granted: April 29, 2014
Patent Number:
8713484
Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the…
Generation, display, and manipulation of measurements in computer graphical designs
Granted: April 29, 2014
Patent Number:
8711177
Display of measurements in a graphical design on a computer system. In one aspect, shapes are displayed in an image, and a definition of a defined area of the image is received. One or more measurements are determined for one or more of the shapes displayed within the predefined area, the one or more measurements determined automatically without a user designating endpoints for the measurements. The one or more measurements are displayed as being associated with the one or more shapes.
System and method for combined I/Q generation and selective phase interpolation
Granted: April 29, 2014
Patent Number:
8710929
A system and method are provided for combined generation of I and Q signal references according to a periodic input signal and selective phase interpolation of an output signal with reference thereto. A ring oscillator portion generates an oscillator signal, and includes a plurality of delay stages interconnected in cascade to collectively execute an odd number of signal state inversions within a closed loop. The delay stages establish at respective nodes defined therebetween…
Method and system for implementing hierarchical prototyping of electronic designs
Granted: April 22, 2014
Patent Number:
8707228
Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.
Synthesis of area-efficient subtractor and divider functional blocks
Granted: April 22, 2014
Patent Number:
8707225
In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of…
Method and apparatus for increasing the efficiency of an emulation engine
Granted: April 22, 2014
Patent Number:
8706469
A method and apparatus for improving the efficiency of a processor-based emulation engine. The emulation engine is composed of a plurality of processors, each processor capable of emulating a logic gate. Processors are arranged into groups of processors called clusters. Each processor receives inputs, processes the inputs, and stores the outputs in an output array. The output array allows processors within a cluster to fetch an output from a processor that was written to the output array…
Methods, systems, and articles of manufactures for implementing electronic circuit designs with IR-drop awareness
Granted: April 15, 2014
Patent Number:
8701067
Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical…
Systems and methods for super-threading of integrated circuit design programs
Granted: April 8, 2014
Patent Number:
8694931
In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a…
Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
Granted: April 8, 2014
Patent Number:
8694933
Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or…
