BLANKET WAFER LASER PRE-EXPOSURE FOR FAST SELECTIVE LAYER TRANSFERS
Granted: March 27, 2025
Application Number:
20250105025
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of integrated circuit (IC) components over the release layer is received, and a second substrate with one or more adhesive areas is received. The release layer on the first substrate is weakened. The first substrate is partially bonded to the second substrate, such that a…
MATERIAL LAYER CONTAINING MOLYBDENUM TO PROTECT GATE DIELECTRIC
Granted: March 27, 2025
Application Number:
20250107209
Techniques are provided to form an integrated circuit having a gate electrode that includes at least one layer containing molybdenum. A transistor includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets) of semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric with at least one of those conductive layers containing molybdenum…
DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
Granted: March 27, 2025
Application Number:
20250107156
Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
METHODS AND ARRANGEMENTS FOR AN N-PATH FILTER USING A FOURTH ORDER ALL POLE DRIVING POINT IMPEDANCE
Granted: March 27, 2025
Application Number:
20250105860
Embodiments may comprise N-path filter circuitry with tunable radio frequency selectivity and up to 80 decibels per decade roll-off. The N-path filter may comprise at least one input transistor, wherein the at least one input transistor comprises a channel and a gate. A first end of the channel is coupled with a receiver circuitry input, wherein a second end of the channel is coupled with a load. The gate of the at least one input transistor is coupled with a clock circuitry input. The…
Techniques For Output Control During Update Of An Integrated Circuit
Granted: March 27, 2025
Application Number:
20250105847
An integrated circuit includes an update controller circuit, updatable logic circuits, and an output circuit. The update controller circuit is configured to control an output signal of the output circuit that is provided to an external conductor during reconfiguration of the updatable logic circuits.
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE LAST APPROACH
Granted: March 27, 2025
Application Number:
20250105222
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having…
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE FIRST APPROACH
Granted: March 27, 2025
Application Number:
20250105209
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE COUPLED TO A GLASS CORE BY INTERCONNECTS
Granted: March 27, 2025
Application Number:
20250105156
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual…
INTEGRATED CIRCUIT STRUCTURES WITH VIAS CONNECTED TO BONDING PADS
Granted: March 27, 2025
Application Number:
20250105139
An example IC structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a…
INTEGRATED CIRCUIT DEVICES WITH VIAS HAVING WIDENED ENDS FOR POWER DELIVERY
Granted: March 27, 2025
Application Number:
20250105095
An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between…
TECHNOLOGIES FOR DUAL TUNABLE LASERS IN A PHOTONIC INTEGRATED CIRCUIT DIE
Granted: March 27, 2025
Application Number:
20250102634
Technologies for tunable lasers in a photonic integrated circuit (PIC) die are disclosed. In an illustrative embodiment, a lidar system includes a PIC die with two lasers. The PIC die includes a switch to switch between the output of the first laser and the output of the second laser. Each laser can be tuned to different peaks of a Bragg grating in the cavity of the laser, and each laser can be frequency swept within the peak of the Bragg grating. In operation, one laser is changed to a…
MEMORY ISOLATION TO IMPROVE SYSTEM RELIABILITY
Granted: March 27, 2025
Application Number:
20250104797
Example systems, apparatus, articles of manufacture, and methods that perform memory preservation to improve system reliability are disclosed. Example apparatus disclosed herein increment an error count after detection of an error associated with a memory cell. Example apparatus also isolate a system memory address of the memory cell based on the error count.
Current Control Systems And Methods For Communications Between Devices
Granted: March 27, 2025
Application Number:
20250104745
An integrated circuit includes a communication controller circuit for exchanging communications with a device external to the integrated circuit through a signal line, a current circuit coupled to the signal line, and a current controller circuit for causing the current circuit to provide a constant current to the signal line while a signal is transmitted through the signal line based on a command generated by the communication controller circuit.
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
Granted: March 27, 2025
Application Number:
20250104180
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
Granted: March 27, 2025
Application Number:
20250104179
A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with…
ARTIFICIAL INTELLIGENCE MODEL PROMPT ADAPTATION IN PROGRAMMABLE NETWORK INTERFACE DEVICES
Granted: March 27, 2025
Application Number:
20250103965
An apparatus includes a host interface, a network interface, and programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors are to implement network interface functionality and are to receive a prompt directed to an artificial intelligence (AI) model hosted by a host device communicably coupled to the host interface, apply a prompt tuning model to the prompt to generate an initial augmented…
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
Granted: March 27, 2025
Application Number:
20250103548
Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
Granted: March 27, 2025
Application Number:
20250103547
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg…
QUALITY OF SERVICE SUPPORT FOR INPUT/OUTPUT AND OTHER AGENTS
Granted: March 27, 2025
Application Number:
20250103397
Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more…
DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS
Granted: March 27, 2025
Application Number:
20250103343
Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing…
