METHODS FOR DOPING 2D TRANSISTOR DEVICES AND RESULTING ARCHITECTURES
Granted: April 3, 2025
Application Number:
20250113599
Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.
EPI HEIGHT REDUCTION FOR IMPROVED TRANSISTOR PERFORMANCE
Granted: April 3, 2025
Application Number:
20250113564
An integrated circuit (IC) device has a stack of nanoribbons between epitaxial source and drain structures with first and second dielectric sections separated by a dielectric layer and adjacent an epitaxial structure. A second dielectric layer may separate a third dielectric section. The dielectric layers may be conformally between the epitaxial structure and the dielectric sections. A height at a top of the epitaxial structure may be reduced, for example, to be very close to a height at…
CONTROLLED RECESS OF DUMMY GATE TO TARGET ACTIVE TRANSISTOR PORTION
Granted: April 3, 2025
Application Number:
20250113516
An integrated circuit (IC) device includes a transistor channel region within (and over a base of) a semiconductor fin, a gate structure over the fin, an isolation or dielectric material adjacent the base of the fin, and an intervening spacer material adjacent the fin, over the dielectric material, and between the channel region (and gate structure) and the isolation or dielectric material. The intervening spacer material may be at substantially equal heights on both sides of the fin.…
FLEXIBLE THERMAL INTERPOSER FOR BACKSIDE COOLING OF DOUBLE-SIDED PACKAGES
Granted: April 3, 2025
Application Number:
20250112106
An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally…
ARCHITECTURES AND METHODS FOR ATTACHING PHOTONIC INTEGRATED CIRCUITS (PICs) TO OPTICAL CONNECTORS
Granted: April 3, 2025
Application Number:
20250110285
Architectures and methods for attaching photonic integrated circuits (PICs) to optical connectors. The architectures are characterized by (1) a cavity at a specific location with respect to a trench alongside an optical facet of the PIC die, (2) index matching epoxy (IME) in the trench and in the cavity, and (3) the use of a snap cure adhesive between the PIC and the optical connector.
INTEGRATED CIRCUIT STRUCTURES WITH VIAS CONNECTED TO BONDING PADS
Granted: March 27, 2025
Application Number:
20250105139
An example IC structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a…
INTEGRATED CIRCUIT DEVICES WITH REPLICA CELLS AND FILLER CELLS FOR REDUCING LOCAL LAYOUT EFFECTS
Granted: March 27, 2025
Application Number:
20250107243
An IC device may include functional regions as well as replica cells and filler cells that can reduce local layout effect in the IC device. A functional region includes functional cells, e.g., logic cell or memory cells. A white space may be between a first functional region and a second functional region. A first portion of the white space may be filled with replica cells, each of which is a replica of a cell in the first functional region. A second portion of the white space may be…
QUANTUM DOT DEVICES
Granted: March 27, 2025
Application Number:
20250107221
Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second…
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
Granted: March 27, 2025
Application Number:
20250107212
Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE COUPLED TO A GLASS CORE BY INTERCONNECTS
Granted: March 27, 2025
Application Number:
20250105156
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual…
TECHNOLOGIES FOR FIBER ARRAY UNIT LID DESIGNS
Granted: March 27, 2025
Application Number:
20250102744
Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the…
INTEGRATED CIRCUIT DEVICES WITH VIAS HAVING WIDENED ENDS FOR POWER DELIVERY
Granted: March 27, 2025
Application Number:
20250105095
An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between…
GLASS CORES INCLUDING PROTRUDING THROUGH GLASS VIAS AND RELATED METHODS
Granted: March 27, 2025
Application Number:
20250105074
Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
CACHE STRUCTURE AND UTILIZATION
Granted: March 27, 2025
Application Number:
20250103546
Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache,…
REGULATING COMMAND SUBMISSION TO A SHARED PERIPHERAL DEVICE
Granted: March 27, 2025
Application Number:
20250103519
Apparatuses, methods, and computer readable media for regulating command submission to a shared device. A processor may receive a command for an operation to be performed by another device. The processor may determine an identifier of an address space of a process associated with the command. The processor may determine whether to accept or reject the command.
TECHNOLOGIES FOR SECURE DEVICE CONFIGURATION AND MANAGEMENT
Granted: March 27, 2025
Application Number:
20250103514
Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution…
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
Granted: March 27, 2025
Application Number:
20250103511
Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has…
SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS
Granted: March 27, 2025
Application Number:
20250103430
Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local…
DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS
Granted: March 27, 2025
Application Number:
20250103343
Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing…
ROBUST WAVEGUIDE ALIGNMENT MECHANISM
Granted: March 27, 2025
Application Number:
20250102745
In one embodiment, a device includes a fiber array unit (FAU) coupled to a photonics integrated circuit (PIC) die. The PIC die includes a cavity defined at an edge of the PIC die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. The PIC die further includes first waveguides protruding into the cavity of the PIC die. The FAU includes a shelf portion extending from a body portion, and a plurality of second…
