AIR GAP INSULATION IN PLACE OF GATE SPACERS
Granted: March 20, 2025
Application Number:
20250098239
IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a S/D region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner…
LOCALIZED THERMAL HEALING AND DOPING OF GLASS CORES FOR MICROELECTRONIC ASSEMBLIES
Granted: March 20, 2025
Application Number:
20250096052
Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second…
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
Granted: March 20, 2025
Application Number:
20250095693
An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit…
MULTI-GRANULAR CLUSTERING-BASED SOLUTION FOR KEY-VALUE CACHE COMPRESSION
Granted: March 20, 2025
Application Number:
20250094712
Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, a multi-granular clustering-based solution for KV cache compression can be implemented. Key tensors and value tensors corresponding unimportant tokens can…
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: March 20, 2025
Application Number:
20250093498
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, a radar system may include a plurality of radar devices. For example, a radar device may include one or more Transmit (Tx) antennas to transmit radar Tx signals, one or more Receive (Rx) antennas to receive radar Rx signals, and a processor to generate radar information based on the radar Rx signals. In one example, the radar system may be implemented as part of a vehicle. In other…
TECHNOLOGIES FOR COLLECTING DELAY RELATED MEASUREMENTS FROM USER PLANE FUNCTIONS USING TRACES
Granted: March 13, 2025
Application Number:
20250088892
This disclosure describes systems, methods, and devices related to optimized delay measurement. A device may receive a request from a consumer to create a Trace job for collecting delay-related measurements from a User Plane Function (UPF). The device may request a Unified Data Management (UDM) system to create the Trace job. The device may receive a response about a result of the Trace job creation from the UDM. The device may send a response indicating the result of the Trace job…
THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE
Granted: March 13, 2025
Application Number:
20250089310
Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third…
GATE CONTACT PATTERNING FOR STATIC RANDOM-ACCESS MEMORY
Granted: March 13, 2025
Application Number:
20250089228
Integrated circuit (IC) structures that include static random-access memory (SRAM) and that are fabricated using gate contact patterning after source/drain (S/D) metallization are disclosed. An example IC structure includes a transistor comprising an S/D region and a gate electrode material, an S/D contact in electrical contact with the S/D region, and a gate contact in electrical contact with the gate electrode material. The S/D contact includes a first electrically conductive material,…
COMPOSITE BACKPLATE ARCHITECTURES FOR BACKSIDE POWER DELIVERY AND ASSOCIATED METHODS
Granted: March 13, 2025
Application Number:
20250089192
Composite backplate architectures for backside power delivery and associated methods are disclosed. An example backplate includes a first layer including a first material, and a second layer attached to the first layer. The second layer includes a second material different from the first material. The example backplate further includes a bus bar attached to the first layer.
POWER SPECTRAL DENSITY LIMIT FOR 6 GHZ
Granted: March 13, 2025
Application Number:
20250088980
This disclosure describes systems, methods, and devices related to power spectral density (PSD) limit. A device may generate a frame comprising one or more elements to be sent to a first station device, wherein the frame is to be sent using a 6 GHz band. The device may include in the frame, information associated with a PSD limit on a per bandwidth size basis of the 6 GHz band. The device may cause to send the frame to the first station device.
ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES
Granted: March 13, 2025
Application Number:
20250086123
In an embodiment, network device apparatus is provided that includes packet processing circuitry to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request, and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, may cause transmission of the memory access request to the different device.…
METHOD AND SYSTEM OF VIDEO CODING WITH CONTENT ADAPTIVE QUANTIZATION
Granted: March 13, 2025
Application Number:
20250088633
Techniques related to video coding include content adaptive quantization that provides a selection between objective quality and subjective quality delta QP offsets. An adaptive method generates an objective quality delta QP offset that achieves a best peak signal-to-noise ratio (PSNR) and/or structural similarity (SSIM) score, which refers to a similarity between images. Also, the adaptive method generates a subjective quality delta QP offset that achieves the best video multi-method…
SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
Granted: March 13, 2025
Application Number:
20250088348
A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled…
LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
Granted: March 13, 2025
Application Number:
20250087530
Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes…
SYSTEMS AND METHODS FOR DISTRIBUTED TRAINING OF DEEP LEARNING MODELS
Granted: March 13, 2025
Application Number:
20250086461
Systems and methods for distributed training of deep learning models are disclosed. An example local device to train deep learning models includes a reference generator to label input data received at the local device to generate training data, a trainer to train a local deep learning model and to transmit the local deep learning model to a server that is to receive a plurality of local deep learning models from a plurality of local devices, the server to determine a set of weights for a…
INNER PRODUCT CONVOLUTIONAL NEURAL NETWORK ACCELERATOR
Granted: March 13, 2025
Application Number:
20250086445
A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct…
DEPLOYMENT OF RESOURCES IN MIXTURE OF EXPERTS PROCESSING
Granted: March 13, 2025
Application Number:
20250086424
Deployment of resources utilizing improved mixture of experts processing is described. An example of an apparatus includes one or more network ports; one or more direct memory access (DMA) engines; and circuitry for mixture of experts (MoE) processing in the network, wherein the circuitry includes at least circuitry to track routing of tokens in MoE processing, prediction circuitry to generate predictions regarding MoE processing, including predicting future token loads for MoE…
METHODS AND APPARATUS FOR CROSSTALK-BASED CLOSED-FORM EXPRESSION FOR IMPROVED PRINTED CIRCUIT BOARD (PCB) DESIGNS
Granted: March 13, 2025
Application Number:
20250086370
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify crosstalk between a first signal via and a second signal via on a printed circuit board (PCB) layout, determine an area for placement of a ground via between the first signal via and the second signal via, and classify one or more regions of the PCB layout into at least one of a protective area or a…
SCALABLE TRUSTED PLATFORM MODULE IN PROGRAMMABLE NETWORK INTERFACE DEVICES
Granted: March 13, 2025
Application Number:
20250086284
An apparatus includes a host interface, a network interface, and a programmable circuitry communicably coupled to the host interface and the network interface. The programmable circuitry can include one or more processors to implement network interface functionality, and a discrete trusted platform module (dTPM) to enable the one or more processors to establish a secure boot mechanism for the apparatus, wherein the one or more processors are to instantiate a virtual TPM (vTPM) manager…
NEURAL NETWORK ACCELERATOR WITH MEMORY HAVING BANK-SPECIFIC CLOCK DOMAIN CROSSING BUFFERS
Granted: March 13, 2025
Application Number:
20250086125
An accelerator may include one or more data processing units that perform deep learning operations in neural networks. A data processing unit includes a memory and a compute engine. The memory may include memory banks and clock domain crossing (CDC) buffers. Each memory bank may have its own CDC buffer(s). The memory banks may be grouped into bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank…
