STACKED MEMORY LAYERS WITH UNIFORM ACCESS
Granted: March 27, 2025
Application Number:
20250107107
An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers.…
INTEGRATED CIRCUIT STRUCTURES WITH VIAS CONNECTED TO BONDING PADS
Granted: March 27, 2025
Application Number:
20250105139
An example IC structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a…
GLASS CORES INCLUDING PROTRUDING THROUGH GLASS VIAS AND RELATED METHODS
Granted: March 27, 2025
Application Number:
20250105074
Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
Granted: March 27, 2025
Application Number:
20250103511
Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has…
DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS
Granted: March 27, 2025
Application Number:
20250103343
Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing…
TECHNIQUES FOR ARTIFICIAL INTELLIGENCE CAPABILITIES AT A NETWORK SWITCH
Granted: March 20, 2025
Application Number:
20250097120
Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.
MITIGATING PROXIMITY EFFECTS OF DEEP TRENCH VIAS
Granted: March 20, 2025
Application Number:
20250098249
Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below…
AIR GAP INSULATION IN PLACE OF GATE SPACERS
Granted: March 20, 2025
Application Number:
20250098242
IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a source or drain (S/D) region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact…
AIR GAP INSULATION IN PLACE OF GATE SPACERS
Granted: March 20, 2025
Application Number:
20250098239
IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a S/D region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner…
METHODS AND APPARATUS FOR ARTIFICIAL INTELLIGENCE (AI) MODEL SECURITY PROTECTION USING MOVING TARGET DEFENSES
Granted: March 20, 2025
Application Number:
20250097249
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in…
MULTI-GRANULAR CLUSTERING-BASED SOLUTION FOR KEY-VALUE CACHE COMPRESSION
Granted: March 20, 2025
Application Number:
20250094712
Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, a multi-granular clustering-based solution for KV cache compression can be implemented. Key tensors and value tensors corresponding unimportant tokens can…
MICROELECTRONIC ASSEMBLIES
Granted: March 20, 2025
Application Number:
20250096194
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts…
MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)
Granted: March 20, 2025
Application Number:
20250096178
Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal…
MICROELECTRONIC ASSEMBLY WITH BRIDGE DIE AND SELECTIVE METALLIZATION LAYERS
Granted: March 20, 2025
Application Number:
20250096143
A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped…
MICROELECTRONIC ASSEMBLIES HAVING A BRIDGE DIE OVER A GLASS PATCH
Granted: March 20, 2025
Application Number:
20250096053
A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an…
LOCALIZED THERMAL HEALING AND DOPING OF GLASS CORES FOR MICROELECTRONIC ASSEMBLIES
Granted: March 20, 2025
Application Number:
20250096052
Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second…
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
Granted: March 20, 2025
Application Number:
20250095693
An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit…
IMAGING FOR FOLDABLE DISPLAYS
Granted: March 20, 2025
Application Number:
20250095522
A processing unit, comprising a display interface to control a foldable display with multiple segments created by fold lines in the foldable display. The processing unit also including a plurality of lanes to connect the display interface to the foldable display, where each segment of the foldable display is connected to a lane. The processing unit also including a multi-segment protocol component to instruct the display interface to drive data to each segment of the display through the…
DISTORTION MESHES AGAINST CHROMATIC ABERRATIONS
Granted: March 20, 2025
Application Number:
20250095122
Described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. The plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. The plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic…
PAGE FAULTING AND SELECTIVE PREEMPTION
Granted: March 20, 2025
Application Number:
20250095099
One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at…
