MULTI-LINK DEVICE DATA CONTINUITY
Granted: March 6, 2025
Application Number:
20250081266
This disclosure describes systems, methods, and devices related to multi-link device (MLD) data continuity. An MLD device may set up one or more links with a station multi-link device (STA MLD), wherein the STA MLD comprises one or more logical entities defining separate station devices. The MLD device may transmit a data packet associated with a traffic identifier (TID) to the STA MLD. The MLD device may determine that the data packet was not received by the STA MLD. The MLD device may…
PACKAGE ARCHITECTURE WITH PACKAGE SUBSTRATE HAVING BLIND CAVITY WITH ROUTING ON SIDEWALLS
Granted: March 6, 2025
Application Number:
20250079266
Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is…
APPARATUS, METHOD, DEVICE AND MEDIUM FOR LABEL-BALANCED CALIBRATION IN POST-TRAINING QUANTIZATION OF DNN
Granted: March 6, 2025
Application Number:
20250077861
The disclosure provides an apparatus, method, device and medium for label-balanced calibration in post-training quantization of DNNs. An apparatus includes interface circuitry configured to receive a training dataset and processor circuitry coupled to the interface circuitry. The processor circuitry is configured to generate a small ground truth dataset by selecting images with a ground truth number of 1 from the training dataset; generate a calibration dataset randomly from the training…
INTEGRATED CIRCUIT PACKAGE SUPPORTS
Granted: February 27, 2025
Application Number:
20250069902
Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second…
RECESSED VIA WITH CONDUCTIVE LINK TO ADJACENT CONTACT
Granted: February 27, 2025
Application Number:
20250072069
Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure…
COLD PLATE ARCHITECTURE FOR LIQUID COOLING OF DEVICES
Granted: February 27, 2025
Application Number:
20250071938
Examples described herein relate to a cold plate. An example apparatus includes a first layer with one or more channels to receive fluid. The example apparatus further includes a second layer that is more rigid than the first layer. The second layer is to be mounted to the first layer and separated from the first layer by a gasket to reduce corrosion of the second layer.
Tall DIMM Structural Retention
Granted: February 27, 2025
Application Number:
20250071924
Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.
RADIO FREQUENCY FRONT-END STRUCTURES
Granted: February 27, 2025
Application Number:
20250071885
Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
MANAGEMENT OF DATA TRANSFER FOR NETWORK OPERATION
Granted: February 27, 2025
Application Number:
20250071037
Management of data transfer for network operation is described. An example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or…
APPARATUS, SYSTEM, AND METHOD OF CHANNEL SOUNDING OVER A WIDE CHANNEL BANDWIDTH
Granted: February 27, 2025
Application Number:
20250070926
For example, a wireless communication device may be configured to generate a wide bandwidth Long Training Field (LTF) configured for channel sounding over a wide channel bandwidth of at least 320 Megahertz (MHz). For example, the wide bandwidth LTF may include a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols over the wide channel bandwidth. For example, the wireless communication device may be configured to transmit a Null Data Packet (NDP) over the wide channel…
POWER OPTIMIZED MULTI-REGIONAL UPDATE DISPLAY
Granted: February 27, 2025
Application Number:
20250069539
In one embodiment, a display panel may have multiple regions that are controlled by independent driver circuitries to allow for independent refreshing of different regions. Circuitry, e.g., in a graphics source or in the display, can determine, based on a partial frame update, which panel regions to refresh and refresh those regions, e.g., while not refreshing other regions of the panel.
GRAPHICS ANTI-ALIASING RESOLVE WITH STENCIL MASK
Granted: February 27, 2025
Application Number:
20250069182
An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
REGION-BASED DETERMINISTIC MEMORY SAFETY
Granted: February 27, 2025
Application Number:
20250068776
Methods and apparatus relating to techniques for region-based deterministic memory safety are described. In some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. The portion of the data is stored in a first region of the memory. The first region of the memory includes a plurality of identically sized allocation slots. Other embodiments are also disclosed and claimed.
SCALAR CORE INTEGRATION
Granted: February 27, 2025
Application Number:
20250068588
Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor…
Secure Shared Memory Buffer For Communications Between Trusted Execution Environment Virtual Machines
Granted: February 27, 2025
Application Number:
20250068556
A system includes memory circuitry to store a secure shared memory buffer (SSMB) and instructions; and a processor to create the SSMB in the memory circuitry and assign ownership of the SSMB to an SSMB owner, the SSMB owner being a trusted execution environment virtual machine running on the computing system; configure access permissions for the SSMB by the SSMB owner to allow one or more SSMB users to access the SSMB, the one or more SSMB users being trusted execution environment…
DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS
Granted: February 27, 2025
Application Number:
20250068473
Described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second…
COMPUTER VISION PIPELINE MANAGEMENT IN PROGRAMMABLE NETWORK INTERFACE DEVICE
Granted: February 27, 2025
Application Number:
20250068457
An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface…
AUTONOMOUS GENERATION OF NETWORK AND DEVICE CONFIGURATIONS
Granted: February 27, 2025
Application Number:
20250068438
Described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. Additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.
INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER THREAD
Granted: February 27, 2025
Application Number:
20250068423
Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.
USER IDENTIFICATION WITH AUDIO EARBUDS
Granted: February 20, 2025
Application Number:
20250061904
Techniques are provided herein for identifying the user of audio earbuds. In particular, a wearer's head filters an audio signal, and the audio filtering capabilities of a user's head are used as a biometric feature. One earbud can be used as an audio emitter and the other earbud as an audio receiver. A broadband sound can be generated by the speaker in one earbud and received at the microphone of the other earbud. The received sound is filtered by the user's head and the head…
