MISUSE INDEX FOR EXPLAINABLE ARTIFICIAL INTELLIGENCE IN COMPUTING ENVIRONMENTS
Granted: February 20, 2025
Application Number:
20250061332
A mechanism is described for facilitating misuse index for explainable artificial intelligence in computing environments, according to one embodiment. A method of embodiments, as described herein, includes mapping training data with inference uses in a machine learning environment, where the training data is used for training a machine learning model. The method may further include detecting, based on one or more policy/parameter thresholds, one or more discrepancies between the training…
NETWORK RESOURCE MODELS AND TECHNOLOGIES FOR ACTIONS EXECUTED ACCORDING TO MACHINE LEARNING INFERENCE REPORTS
Granted: February 20, 2025
Application Number:
20250062967
This disclosure describes systems, methods, and devices related to optimized resource technologies. A device may create a Managed Object Instance (MOI) representing actions executed based on artificial intelligence or machine learning (AI/ML) inference function. The device may notify a management and network service (MnS) consumer about the creation of the MOI. The device may execute actions by a network or management function acting as the consumer of the inference output. The device…
ENHANCED CODE RATE REDUCTION FOR PROBABILISTIC CONSTELLATION SHAPING IN WIRELESS COMMUNICATIONS
Granted: February 20, 2025
Application Number:
20250062946
This disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (QAM) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (FEC) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel,…
APPARATUS, SYSTEM, AND METHOD OF CONFIGURING RATE-DEPENDENT PARAMETERS FOR TRANSMISSION OF A PHYSICAL LAYER (PHY) PROTOCOL DATA UNIT (PPDU)
Granted: February 20, 2025
Application Number:
20250062855
For example, a wireless communication station (STA) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a Physical layer (PHY) Protocol Data Unit (PPDU) based on a minimal Medium Access Control (MAC) Protocol Data Unit (MPDU) size requirement such that, for at least one MPDU of the PPDU, a first count of MAC padding bits to pad the MPDU according to the selected setting of the one or more rate-dependent parameters is less than a…
APPARATUS, SYSTEM, AND METHOD OF CURRENT CONSUMPTION ADJUSTMENT
Granted: February 20, 2025
Application Number:
20250062610
For example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. For example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. For example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the…
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER INTERCONNECTS
Granted: February 20, 2025
Application Number:
20250062278
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically…
METHODS AND APPARATUS TO REDUCE CRACKING IN GLASS CORES
Granted: February 20, 2025
Application Number:
20250062207
Methods and apparatus to reduce cracking in glass cores are disclosed. An example apparatus includes a package substrate comprising a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface, and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first…
PACKAGE ARCHITECTURE WITH BRIDGE DIES HAVING AIR GAPS AROUND VIAS
Granted: February 20, 2025
Application Number:
20250062206
Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies…
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
Granted: February 20, 2025
Application Number:
20250061535
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other…
PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH ADVANCED SCHEDULING
Granted: February 20, 2025
Application Number:
20250061534
One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the…
SUB-SURFACE COMPOUND MICROLENSES
Granted: February 20, 2025
Application Number:
20250060516
Photonic devices, packages, and systems with sub-surface compound microlenses are disclosed. An example microlens structure includes a glass core and a microlens stack embedded in the glass core, the stack comprising a plurality of regions stacked a direction of propagation of light that is to be manipulated by the microlens structure, wherein each region is a region of a substantially uniform refractive index that is different from the refractive index of the glass core. Such a stack…
SCALING HALF-PRECISION FLOATING POINT TENSORS FOR TRAINING DEEP NEURAL NETWORKS
Granted: February 20, 2025
Application Number:
20250061318
One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network…
METHODS AND APPARATUS FOR ENABLING EFFICIENT FINE-TUNING ON UNSTRUCTURED SPARSE AND LOW-PRECISION LARGE PRE-TRAINED FOUNDATION MODELS
Granted: February 20, 2025
Application Number:
20250061317
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to sparsify a base model of a foundation model to generate a sparse base model, apply a neural low-rank adapter search to the sparse base model, and output a fine-tuned base model based on application of the neural low-rank adapter search to the sparse base model.
METHODS AND APPARATUS FOR DISTRIBUTED USE OF A MACHINE LEARNING MODEL
Granted: February 20, 2025
Application Number:
20250061229
Methods, apparatus, systems and articles of manufacture for distributed use of a machine learning model are disclosed. An example edge device includes a model partitioner to partition a machine learning model received from an aggregator into private layers and public layers. A public model data store is implemented outside of a trusted execution environment of the edge device. The model partitioner is to store the public layers in the public model data store. A private model data store…
DEVICE RUNTIME UPDATE PRE-AUTHENTICATION
Granted: February 20, 2025
Application Number:
20250061203
A method comprises establishing, in a trusted security manager of a trusted execution environment, a device update pre-authentication policy for a device communicatively coupled to the trusted execution manager, providing the device update pre-authentication policy to the device, receiving, from the device, a pre-authentication event signal, and providing, to the device, a pre-authentication event response comprising an update indicator to indicate to the device whether a runtime update…
METHOD AND APPARATUS OF SPATIALLY SPARSE CONVOLUTION MODULE FOR VISUAL RENDERING AND SYNTHESIS
Granted: February 20, 2025
Application Number:
20250061172
Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output…
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHERENCY IN A HETEROGENEOUS PROCESSING SYSTEM
Granted: February 20, 2025
Application Number:
20250061060
Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory…
METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF A COMPUTING DEVICE IMPLEMENTING AN EXPONENTIAL FUNCTION
Granted: February 20, 2025
Application Number:
20250060941
Systems, apparatus, articles of manufacture, and methods are disclosed to improve performance of a computing device implementing an exponential function. An example apparatus includes interface circuitry to obtain an input, computer readable instructions, and programmable circuitry to instantiate range reduction circuitry to determine, based on the input, a first range reduced argument and an accuracy control value for an approximation of the exponential function of the neural network,…
NEURAL NETWORK ACCELERATOR PERFORMING OPERATION WITH MIXED-FORMAT WEIGHTS
Granted: February 20, 2025
Application Number:
20250060940
A data processing unit may include a memory, processing elements (PEs), and a control unit. The memory may store weight blocks within a weight tensor of a neural network operation. Each weight block has an input channel (IC) dimension and an output channel (OC) dimension and includes subblocks. A subblock includes one or more weights having a first data precision and one or more other weights having a second data precision. The second data precision is lower than the first data…
PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURE
Granted: February 20, 2025
Application Number:
20250060531
Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and…
