HANDLING PRE-ASSOCIATION EXCHANGES WITH EXTENDED LONG RANGE OPERATION
Granted: February 20, 2025
Application Number:
20250063612
This disclosure describes systems, methods, and devices related to pre-association exchange. A device may receive a physical layer (PHY) based extended long range (ELR) request from a station device (STA) within a transmission opportunity (TxOP). The device may allocate a unique Unassociated ID (UID) to the STA within the same TxOP, the UID being distinct among active unassociated devices. The device may indicate to the STA to use the UID in subsequent communications until association or…
APPARATUS, SYSTEM, AND METHOD OF CONFIGURING RATE-DEPENDENT PARAMETERS FOR TRANSMISSION OF A PHYSICAL LAYER (PHY) PROTOCOL DATA UNIT (PPDU)
Granted: February 20, 2025
Application Number:
20250062855
For example, a wireless communication station (STA) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a Physical layer (PHY) Protocol Data Unit (PPDU) based on a minimal Medium Access Control (MAC) Protocol Data Unit (MPDU) size requirement such that, for at least one MPDU of the PPDU, a first count of MAC padding bits to pad the MPDU according to the selected setting of the one or more rate-dependent parameters is less than a…
USER IDENTIFICATION WITH AUDIO EARBUDS
Granted: February 20, 2025
Application Number:
20250061904
Techniques are provided herein for identifying the user of audio earbuds. In particular, a wearer's head filters an audio signal, and the audio filtering capabilities of a user's head are used as a biometric feature. One earbud can be used as an audio emitter and the other earbud as an audio receiver. A broadband sound can be generated by the speaker in one earbud and received at the microphone of the other earbud. The received sound is filtered by the user's head and the head…
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
Granted: February 20, 2025
Application Number:
20250061535
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other…
METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF A COMPUTING DEVICE IMPLEMENTING AN EXPONENTIAL FUNCTION
Granted: February 20, 2025
Application Number:
20250060941
Systems, apparatus, articles of manufacture, and methods are disclosed to improve performance of a computing device implementing an exponential function. An example apparatus includes interface circuitry to obtain an input, computer readable instructions, and programmable circuitry to instantiate range reduction circuitry to determine, based on the input, a first range reduced argument and an accuracy control value for an approximation of the exponential function of the neural network,…
METHODS AND APPARATUS TO MITIGATE CRACKING IN GLASS CORES
Granted: February 13, 2025
Application Number:
20250054823
Methods and apparatus to mitigate cracking in glass cores are disclosed. An example apparatus comprises a glass core having an opening extending between opposing surfaces of the glass core, and a metal within the opening. a gap between an interface of the metal and a sidewall of the opening.
ENHANCED PRECISION RANGING FOR WI-FI NETWORKS
Granted: February 13, 2025
Application Number:
20250056486
This disclosure describes systems, methods, and devices related to enhanced ranging. A device may initiate a ranging sequence by transmitting an NDPA frame followed by an I2R NDP frame. The device may receive a corresponding R2I NDP frame and an R2I LMR from a responding station. The device may repeat the ranging sequence for two or more iterations to collect multiple data sets. The device may process the R2I NDP frame and the R2I LMR to generate continuous ToA and ToD measurements for…
OFFLOADING VIDEO CODING PROCESSES TO HARDWARE FOR BETTER DENSITY-QUALITY TRADEOFFS
Granted: February 13, 2025
Application Number:
20250055987
Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
PINS FOR USE IN LAND GRID ARRAY
Granted: February 13, 2025
Application Number:
20250055217
A Land Grid Array (LGA) interface assembly used to physically interface or connect a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) and a PCB, motherboard, etc. The LGA interface assembly including an LGA socket including a plurality of socket pins arranged and configured to contact a plurality of contact pads on the semiconductor package to enable data transfer. The socket pins including a multi-bend and/or zig-zag configuration arranged and configured to minimize…
SEMICONDUCTOR DEVICE WITHIN INTERCONNECT STRUCTURE
Granted: February 13, 2025
Application Number:
20250054856
Techniques for forming a semiconductor device (such as a metal-semiconductor-metal device) within the interconnect region over a device layer (such as plurality of field effect transistor (FET) devices). An interconnect layer within a stack of interconnect layers includes a metal-semiconductor-metal (MSM) structure having a first metal layer, a semiconductor layer on the first metal layer, and a second metal layer on the semiconductor layer. The first metal layer may be directly on a…
EFFICIENT SUPER-SAMPLING IN VIDEOS USING HISTORICAL INTERMEDIATE FEATURES
Granted: February 13, 2025
Application Number:
20250050212
Systems and methods for providing a high-resolution gaming experience on typical computer systems, including computer systems without high-end d-GPUs. In particular, systems and methods are provided for optimizing deep learning-based super-sampling methods. A hardware-aware optimization technique for super-sampling machine learning networks uses a subset of intermediate outputs of the machine learning model for the previous game frame for convolution operations on the current frame,…
COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
Granted: February 13, 2025
Application Number:
20250053797
An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.
SCALABLE MULTI-KEY MEMORY ENCRYPTION
Granted: February 13, 2025
Application Number:
20250053668
Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a…
PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS
Granted: February 13, 2025
Application Number:
20250053641
A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active…
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
Granted: February 13, 2025
Application Number:
20250053613
Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.
HIGHLY SCALABLE ACCELERATOR
Granted: February 13, 2025
Application Number:
20250053530
Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all…
EXTENDED ERROR MANAGEMENT WITH CONFIGURABLE HEADER LOGS
Granted: February 13, 2025
Application Number:
20250053470
An example of an apparatus may include a processor to process request transactions and completion transactions for one or more respective communication protocols, memory coupled to the processor to store error-related transaction information, and circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. Other examples are…
METHODS AND APPARATUS FOR A MACHINE LEARNING MODEL DECOMPRESSION ACCELERATOR
Granted: February 13, 2025
Application Number:
20250053454
Systems, apparatus, articles of manufacture, and methods are disclosed for a machine learning model decompression accelerator. An example apparatus includes a processor core including at least one matrix multiplication engine, a memory storing a plurality of tiles of compressed data of a machine learning model to be processed by the at least one matrix multiplication engine; and a decompression accelerator including one or more control registers in communication with the processor core,…
METHODS AND APPARATUS TO SAVE POWER BASED ON USER PRESENCE
Granted: February 13, 2025
Application Number:
20250053221
Systems, apparatus, articles of manufacture, and methods are disclosed to perform power-saving based on user presence, including a network interface to communicate with a cloud device, user presence detector circuitry to determine if a user is present or not present; workload distributor circuitry to distribute an AI workload to either first AI inference circuitry or second AI inference circuitry; and power circuitry to charge a battery at either a first charge level or a second charge…
DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH A THREE-DIMENSIONAL INTEGRATED CIRCUIT
Granted: February 13, 2025
Application Number:
20250052809
Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second…
