OFFLOADING VIDEO CODING PROCESSES TO HARDWARE FOR BETTER DENSITY-QUALITY TRADEOFFS
Granted: February 13, 2025
Application Number:
20250055987
Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
PREAMBLE FOR EXTREMELY HIGH THROUGHPUT TRIGGER BASED PHYSICAL LAYER PROTOCOL DATA UNIT
Granted: February 13, 2025
Application Number:
20250055641
This disclosure describes systems, methods, and devices related to extremely high throughput (EHT) trigger based (TB) preamble. A device may receive a trigger frame from an associated access point (AP), wherein the trigger frame comprises one or more resource unit (RU) bandwidths (BWs) allocated to the device. The device may generate an EHT physical layer protocol data unit (PPDU) based on receiving the trigger frame from the access point, wherein the PPDU comprises an EHT preamble that…
SCALABLE MULTI-KEY MEMORY ENCRYPTION
Granted: February 13, 2025
Application Number:
20250053668
Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a…
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
Granted: February 13, 2025
Application Number:
20250053613
Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.
METHODS AND APPARATUS FOR A MACHINE LEARNING MODEL DECOMPRESSION ACCELERATOR
Granted: February 13, 2025
Application Number:
20250053454
Systems, apparatus, articles of manufacture, and methods are disclosed for a machine learning model decompression accelerator. An example apparatus includes a processor core including at least one matrix multiplication engine, a memory storing a plurality of tiles of compressed data of a machine learning model to be processed by the at least one matrix multiplication engine; and a decompression accelerator including one or more control registers in communication with the processor core,…
METHODS AND APPARATUS TO SAVE POWER BASED ON USER PRESENCE
Granted: February 13, 2025
Application Number:
20250053221
Systems, apparatus, articles of manufacture, and methods are disclosed to perform power-saving based on user presence, including a network interface to communicate with a cloud device, user presence detector circuitry to determine if a user is present or not present; workload distributor circuitry to distribute an AI workload to either first AI inference circuitry or second AI inference circuitry; and power circuitry to charge a battery at either a first charge level or a second charge…
ADAPTIVE QUALITY BOOSTING FOR LOW LATENCY VIDEO CODING
Granted: February 6, 2025
Application Number:
20250047851
Techniques related to adaptive quality boosting for low latency video coding are discussed. Such techniques include segmenting each of a number of temporally adjacent video frames into unique high encode quality regions and encoding each of the video frames by applying a coding quality boost to the high encode quality regions relative to other regions of the video frames.
ENHANCED COMPATIBILITY BETWEEN NEXT-GENERATION ACCESS POINTS AND LEGACY CLIENTS THROUGH WPA3 CAPABILITY ADVERTISING
Granted: February 6, 2025
Application Number:
20250048109
This disclosure describes systems, methods, and devices related to enhanced capability advertising. A device may send a Beacon frame or a Probe Response frame on a legacy band, including an enhanced Security Element containing one or more fields of an original robust security network element (RSNE). The device may override at least one of the one or more fields from the enhanced Security Element over corresponding fields in the original RSNE during a connection establishment process with…
SUPPORT OF AUTHORIZATION OF USER EQUIPMENT BASED SENSING IN A MOBILE SYSTEM
Granted: February 6, 2025
Application Number:
20250048088
This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to…
ACOUSTIC SIGNAL PROCESSING ADAPTIVE TO USER-TO-MICROPHONE DISTANCES
Granted: February 6, 2025
Application Number:
20250048049
Apparatus, systems, methods, and articles of manufacture are disclosed for acoustic signal processing adaptive to microphone distances. An example system includes a microphone to convert an acoustic signal to an electrical signal and one or more processors to: estimate a distance between a source of the acoustic signal and the microphone; select a signal processing mode based on the distance; and process the electrical signal in accordance with the selected processing mode.
REAL-TIME DYNAMIC NOISE REDUCTION USING CONVOLUTIONAL NETWORKS
Granted: February 6, 2025
Application Number:
20250046304
A system, method and computer readable medium for dynamic noise reduction in a voice call. The system includes an encoder having a short-time Fourier transform module to determine a magnitude spectrum and a phase spectrum of an input audio signal. The input audio signal includes speech and dynamic noise. A separator is coupled to the encoder. The separator comprises a temporal convolution network (TCN) used to develop a separation mask using the magnitude spectrum as input. The TCN is…
MULTI-TILE GRAPHICS PROCESSOR RENDERING
Granted: February 6, 2025
Application Number:
20250046001
Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.
DYNAMIC NEURAL NETWORK SURGERY
Granted: February 6, 2025
Application Number:
20250045582
Techniques related to compressing a pre-trained dense deep neural network to a sparsely connected deep neural network for efficient implementation are discussed. Such techniques may include iteratively pruning and splicing available connections between adjacent layers of the deep neural network and updating weights corresponding to both currently disconnected and currently connected connections between the adjacent layers.
METHODS AND APPARATUS TO TILE WALK A TENSOR FOR CONVOLUTION OPERATIONS
Granted: February 6, 2025
Application Number:
20250045560
An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the…
TUNABLE EDGE-COUPLED INTERFACE FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
Granted: February 6, 2025
Application Number:
20250044537
A tunable edge-coupled interface for photonic integrated circuits (PICs). The architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the PIC die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the PIC, (3) actuator beams flanking the waveguide beams, the actuator beams include…
TECHNOLOGIES FOR OPTICAL INTERPOSER MATING WITH PHOTONIC INTEGRATED CIRCUIT DIES
Granted: February 6, 2025
Application Number:
20250044533
In an illustrative embodiment, mechanical adhesive and a separate index-matching material are used as underfill between a photonic integrated circuit (PIC) die and an optical interposer. The index-matching material reduces coupling loss between waveguides of the PIC die and waveguides of the optical interposer, while the mechanical adhesive secures the optical interposer in place. The mechanical adhesive can be thermally cured, have a low coefficient of thermal expansion (CTE), have high…
INTERFEROMETRIC WAVEMETER FOR BROADBAND SENSORS IN PHOTONIC SYSTEMS
Granted: January 30, 2025
Application Number:
20250035425
Disclosed herein are embodiments of a broadband wavemeter system comprising: a laser source to generate an optical signal having one or more wavelengths; a tap to separate a portion of the optical signal from the laser source; a splitter to split an incoming optical signal from the tap into a plurality of outgoing optical signals; a plurality of wavemeters, each one in the plurality to receive one of the outgoing optical signals from the splitter, in which each wavemeter in the plurality…
COMPRESSION FOR SPARSE DATA STRUCTURES UTILIZING MODE SEARCH APPROXIMATION
Granted: January 30, 2025
Application Number:
20250036608
Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and…
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
Granted: January 30, 2025
Application Number:
20250036361
Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format…
LOW LOSS SPLITTER-COMBINER WAVEGUIDE STRUCTURES IN PHOTONIC CIRCUITS
Granted: January 30, 2025
Application Number:
20250035838
Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.
