SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS
Granted: January 30, 2025
Application Number:
20250036451
An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
ACKNOWLEDGMENT PROTOCOL PROTECTION
Granted: January 30, 2025
Application Number:
20250039670
This disclosure describes systems, methods, and devices related to enhanced wireless frame security. A device may utilize a Galois Message Authentication Code with a 256-bit key (GMAC-256) as an integrity protocol for block acknowledgment (BA) and block acknowledgment request (BAR). The device may generate a packet number (PN) and Message Integrity Code (MIC) using GMAC-256 for integrity design in the BA and BAR. The device may include a key identification (ID) indication in a BA control…
ENHANCED PERFORMANCE AND EFFICIENCY OF VERSATILE VIDEO CODING DECODER PIPELINE FOR ADVANCED VIDEO CODING FEATURES
Granted: January 30, 2025
Application Number:
20250039469
This disclosure describes systems, methods, and devices related to enhanced video coding. A device may receive encoded bitstream data of a frame with multiple tiles. The device may divide each tile into multiple coding tree units (CTUs). The device may decode Luma and Chroma pixels of each CTU using either a single-tree mode or a dual-tree mode. The device may execute a cross-component linear model (CCLM) prediction to predict Chroma pixels based on decoded Luma pixels. The device may…
METHOD AND SYSTEM OF EVALUATION OF AUDIO DEVICE SUSCEPTIBILITY TO ULTRASONIC ATTACK
Granted: January 30, 2025
Application Number:
20250038879
A system, article, device, apparatus, and method of audio processing comprises receiving, by processor circuitry, audible audio signal data of intermodulation distortion products (IDPs) based on ultrasonic audio signals received by at least one microphone of an audio device. The method also compares the audible audio signal data to ultrasonic audio signal data of the ultrasonic audio signals. Thereafter, the method determines a plurality of susceptibility values each of a different…
ADAPTIVE MULTISAMPLING BASED ON VERTEX ATTRIBUTES
Granted: January 30, 2025
Application Number:
20250037359
Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.
32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLIERS PER-CHANNEL
Granted: January 30, 2025
Application Number:
20250037347
Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single…
PERFORMANCE SCALING FOR DATAFLOW DEEP NEURAL NETWORK HARDWARE ACCELERATORS
Granted: January 30, 2025
Application Number:
20250036928
Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of…
NETWORK INTERFACE DEVICE-BASED MEMORY ACCESS TO REDUCE WRITE AMPLIFICATION FACTOR AND PROVIDE ATTESTATION
Granted: January 30, 2025
Application Number:
20250036783
An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function…
COMPRESSION FOR SPARSE DATA STRUCTURES UTILIZING MODE SEARCH APPROXIMATION
Granted: January 30, 2025
Application Number:
20250036608
Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and…
MICROSERVICE PROVISION AND MANAGEMENT
Granted: January 30, 2025
Application Number:
20250036477
A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKED REGISTER FORMATS
Granted: January 30, 2025
Application Number:
20250036412
Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data…
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
Granted: January 30, 2025
Application Number:
20250036361
Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format…
LOW LOSS SPLITTER-COMBINER WAVEGUIDE STRUCTURES IN PHOTONIC CIRCUITS
Granted: January 30, 2025
Application Number:
20250035838
Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.
PROCESSORS, METHODS AND SYSTEMS TO ALLOW SECURE COMMUNICATIONS BETWEEN PROTECTED CONTAINER MEMORY AND INPUT/OUTPUT DEVICES
Granted: January 23, 2025
Application Number:
20250028455
An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an…
ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONTSIDE AND BACKSIDE OF A STACKED TRANSISTOR STRUCTURE
Granted: January 23, 2025
Application Number:
20250031362
Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a…
VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC SPACERS
Granted: January 23, 2025
Application Number:
20250029915
Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may…
METHOD AND APPARATUS FOR VIEWPORT SHIFTING OF NON-REAL TIME 3D APPLICATIONS
Granted: January 23, 2025
Application Number:
20250029312
Systems and methods for super sampling and viewport shifting of non-real time 3D applications are disclosed. In one embodiment, a graphics processing unit includes a processing resource to execute graphics commands to provide graphics for an application, a capture tool to capture the graphics commands, and a data generator to generate a dataset including at least one frame based on the captured graphics commands and to modify viewport settings for each frame of interest to generate a…
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
Granted: January 23, 2025
Application Number:
20250028675
Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end…
SYSTEM CACHE OPTIMIZATIONS FOR DEEP LEARNING COMPUTE ENGINES
Granted: January 23, 2025
Application Number:
20250028650
In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.
SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS
Granted: January 23, 2025
Application Number:
20250028565
Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. The present disclosure provides a schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators, wherein the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime.…
