IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT
Granted: April 3, 2025
Application Number:
20250112187
A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the…
SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS
Granted: April 3, 2025
Application Number:
20250112218
In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the…
FINE-GRAIN INTEGRATION OF RADIO FREQUENCY AND HIGH-VOLTAGE DEVICES
Granted: April 3, 2025
Application Number:
20250112216
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic…
FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES
Granted: April 3, 2025
Application Number:
20250112210
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is…
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
Granted: April 3, 2025
Application Number:
20250112208
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
DIE-TO-DIE INPUT/OUTPUT SIGNAL ROUTING UTILIZING OPPOSING DIE SURFACES IN INTEGRATED CIRCUIT COMPONENT PACKAGING
Granted: April 3, 2025
Application Number:
20250112205
Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid…
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112200
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
IN-CAVITY EPOXY PLACEMENT FOR PACKAGE RELIABILITY
Granted: April 3, 2025
Application Number:
20250112198
An apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. Other embodiments are also disclosed and claimed.
SELF-DIFFUSING LIQUID METAL INTERCONNECT ARCHITECTURES ENABLING SNAP-ON ROOM TEMPERATURE ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112190
In one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. The substrate includes first reservoirs comprising Gallium-based liquid metal (LM), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. The component includes circuitry and conductive contacts connected to the circuitry. Each contact defines a cavity and a portion of each conductive…
FINE-GRAIN INTEGRATION OF RADIO FREQUENCY ANTENNAS, INTERCONNECTS, AND PASSIVES
Granted: April 3, 2025
Application Number:
20250112188
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is…
POLYETHYLENE OXIDE-BASED OPTICAL ADHESIVE
Granted: April 3, 2025
Application Number:
20250110295
A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE
Granted: April 3, 2025
Application Number:
20250112186
A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a…
BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASSISTED ASSEMBLY OF INTEGRATED CIRCUIT DIE STACKS
Granted: April 3, 2025
Application Number:
20250112181
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces…
SEMICONDUCTOR DESIGN LITHOGRAPHIC SEAM IMPLEMENTATION METHODOLOGY FOR ADVANCED TECHNOLOGIES
Granted: April 3, 2025
Application Number:
20250112167
An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as…
DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112162
An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is…
PARTITIONED HOME SNOOP FILTER
Granted: April 3, 2025
Application Number:
20250110879
Techniques for partitioned home snoop filtering are described. In an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. The home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
INSTRUCTION BLOCK BASED PERFORMANCE MONITORING
Granted: April 3, 2025
Application Number:
20250110739
Techniques for block based performance monitoring are described. In an embodiment, an apparatus includes execution hardware to execute a plurality of instructions; and block-based sampling hardware. The block-based sampling hardware is to identify, based on a first branch instruction of the plurality of instructions and a second branch instruction of the plurality of instructions, a block of instructions; and to collect, during execution of the block of instructions, performance…
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS
Granted: April 3, 2025
Application Number:
20250110737
An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf…
METHODS AND APPARATUS TO REDUCE MEMORY POWER CONSUMPTION
Granted: April 3, 2025
Application Number:
20250110541
An example apparatus includes memory; machine-readable instructions; and at least one programmable circuit to at least one of execute or instantiate the machine-readable instructions to at least adjust a frequency of a clock signal of the memory based on workload demands of a processor circuit.
TECHNOLOGIES FOR THERMAL PLUGS IN A PHOTONIC INTEGRATED CIRCUIT DIE
Granted: April 3, 2025
Application Number:
20250110301
Technologies for thermal plugs in photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, several thermal plugs extend from contact pads in a PIC die, through a dielectric layer, to a waveguide layer. The thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the PIC die. The PIC die may be mounted on an electronic integrated circuit (EIC) die in an integrated circuit component. The PIC die…
