Systems And Methods With Auxiliary Control Boards Having Interface Devices
Granted: November 28, 2024
Application Number:
20240393848
A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security…
OFFSET VOIDING SCHEME FOR VERTICAL INTERCONNECTS
Granted: November 28, 2024
Application Number:
20240397610
An integrated circuit (IC) package includes a via extending through a stack of antipads in a stack of layers, and the stack of antipads has an antipad with a shorter diameter between antipads with longer diameters. The via may have first and second connections and first and second pads at or over and under the antipads. The longer diameters (over and under the shorter diameter) may be equal. Intervening antipads of intermediate size may be between the smallest antipads and the largest…
ENHANCED PERFORMANCE MEASUREMENTS RELATED TO ONE-WAY UPLINK PACKET DELAY IN WIRELESS COMMUNICATIONS
Granted: November 28, 2024
Application Number:
20240397362
This disclosure describes systems, methods, and devices for performing performance measurements for one-way uplink packet delay in wireless communications. An apparatus of a Service Based Management Architecture (SBMA) Management Service (MnS) Producer may identify performance measurements, received from a network function (NF) of a 5th Generation (5G) wireless network, indicative of uplink packet delay between a user equipment (UE) and a protocol data unit (PDU) session anchor (PSA)…
ACCELERATED NETWORK PACKET PROCESSING
Granted: November 28, 2024
Application Number:
20240396980
Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.
SCALABLE EDGE COMPUTING
Granted: November 28, 2024
Application Number:
20240396852
There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI…
MULTI-TENANCY PROTECTION FOR ACCELERATORS
Granted: November 28, 2024
Application Number:
20240396711
An accelerator includes a memory, a compute zone to receive an encrypted workload downloaded from a tenant application running in a virtual machine on a host computing system attached to the accelerator, and a processor subsystem to execute a cryptographic key exchange protocol with the tenant application to derive a session key for the compute zone and to program the session key into the compute zone. The compute zone is to decrypt the encrypted workload using the session key, receive…
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF POSITIVE CURRENT
Granted: November 28, 2024
Application Number:
20240396327
An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of positive current.
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF NEGATIVE CURRENT
Granted: November 28, 2024
Application Number:
20240395800
An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of negative current.
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH ULTRA LOW-LEAKAGE
Granted: November 28, 2024
Application Number:
20240395798
An electrostatic discharge protection circuit, device, system, and apparatus has ultra-low-leakage.
SELECTIVE UNDERFILLING USING PRE-APPLIED THERMOSET ADHESIVE
Granted: November 28, 2024
Application Number:
20240395567
Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: November 21, 2024
Application Number:
20240385291
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, a plurality of Receive (Rx) antennas to receive radar Rx signals based on the Tx signals, and a processor to generate radar information based on the radar Rx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar…
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
Granted: November 21, 2024
Application Number:
20240389300
A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different…
THREE-DIMENSIONAL FOLDED STATIC RANDOM-ACCESS MEMORY
Granted: November 21, 2024
Application Number:
20240389294
Described herein are SRAM cells in which some transistors are implemented as thin film transistors (TFTs) while other transistors are implemented as non-TFTs (e.g., as FinFETs or nanoribbon-based transistors), where the TFTs are folded over non-TFTs to realize high-density 3D SRAM. For a given SRAM cell, either N-type transistors may be implemented as TFTs and stacked above P-type transistors that are implemented as non-TFTs, or P-type transistors may be implemented as TFTs and may be…
APPARATUS AND SYSTEM OF ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING
Granted: November 21, 2024
Application Number:
20240389289
For example, an apparatus may include an Electromagnetic Interference (EMI) shield, which may be configured to provide EMI shielding for electronic circuitry on a Printed Circuit Board (PCB). For example, the EMI shield may be configured to include an EMI shield lid; and an EMI shield connector to electrically couple the EMI shield lid to at least one tube on the PCB to provide a ground to the EMI shield lid via the at least one tube. For example, the EMI shield connector may be…
Server, Client, Methods and Program Codes
Granted: November 21, 2024
Application Number:
20240388494
A server is provided. The server comprises one or more interfaces configured to communicate with a client and processing circuitry configured to control the one or more interfaces and to transmit an interrupt to the client informing the client about an operation state of the server.
System and Method for High Performance Secure Access to a Trusted Platform Module on a Hardware Virtualization Platform
Granted: November 21, 2024
Application Number:
20240388439
A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating…
MODEL OPTIMIZATION IN INFRASTRUCTURE PROCESSING UNIT (IPU)
Granted: November 21, 2024
Application Number:
20240386272
An Infrastructure Processing Unit (IPU), including: a model optimization processor configured to optimize an artificial intelligence (AI) model for an accelerator managed by the IPU, and deploy the optimized AI model to the accelerator for execution of an inference; and a local memory configured to store data related to the AI model optimization.
EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS
Granted: November 21, 2024
Application Number:
20240385975
An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry…
SENSOR-BASED CONTROL FOR DEBUG INVASIVENESS
Granted: November 21, 2024
Application Number:
20240385946
An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.
DYNAMIC RESOURCE MANAGEMENT MECHANISM
Granted: November 21, 2024
Application Number:
20240385901
A computing platform is disclosed. The computing platform includes a first computer system comprising a first graphics processing unit (GPU), a network coupled to the first computer system and a second computer system, coupled to the first computer system via the network, comprising a second GPU, wherein the first and second computer system are configured to perform distributed processing of graphics workloads between the first GPU and the second GPU.
