EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING
Granted: April 18, 2024
Application Number:
20240128138
Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first…
TECHNOLOGIES FOR A FLEXIBLE 3D POWER PLANE IN A CHASSIS
Granted: April 18, 2024
Application Number:
20240130068
Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board…
TECHNOLOGIES FOR WIRELESS SENSOR NETWORKS
Granted: April 18, 2024
Application Number:
20240130002
Various technologies relating to wireless sensor networks (WSNs) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.
APPARATUS, SYSTEM, AND METHOD OF QUALITY OF SERVICE (QOS) NETWORK SLICING OVER WIRELESS LOCAL AREA NETWORK (WLAN)
Granted: April 18, 2024
Application Number:
20240129804
For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing…
Lossless Compression for Multisample Render Targets Alongside Fragment Compression
Granted: April 18, 2024
Application Number:
20240129503
Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing…
APPARATUS, SYSTEM AND METHOD OF AN ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING (OFDM) TRANSMISSION OVER A WIDE BANDWIDTH
Granted: April 18, 2024
Application Number:
20240129058
For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over…
HARDWARE ACCELERATION OF DATA REDUCTION OPERATIONS
Granted: April 18, 2024
Application Number:
20240128982
A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
INTEGRATED CIRCUIT CONTACT STRUCTURES
Granted: April 18, 2024
Application Number:
20240128340
Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.
MICROELECTRONIC ASSEMBLIES
Granted: April 18, 2024
Application Number:
20240128255
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts…
PACKAGE ARCHITECTURE WITH GLASS CORE SUBSTRATE HAVING INTEGRATED INDUCTORS
Granted: April 18, 2024
Application Number:
20240128247
Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly…
POWER OPTIMIZED BLEND
Granted: April 18, 2024
Application Number:
20240126357
Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.
DECOUPLING CAPACITORS BASED ON DUMMY THROUGH-SILICON-VIAS
Granted: April 18, 2024
Application Number:
20240128023
Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching,…
TECHNOLOGIES FOR FUSING DATA FROM MULTIPLE SENSORS TO IMPROVE OBJECT DETECTION, IDENTIFICATION, AND LOCALIZATION
Granted: April 18, 2024
Application Number:
20240127478
Technologies for performing sensor fusion include a compute device. The compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. The detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. The circuitry is also configured to merge the detection data from the multiple sensors to…
SYSTEMS AND METHODS FOR TONE MAPPING OF HIGH DYNAMIC RANGE IMAGES FOR HIGH-QUALITY DEEP LEARNING BASED PROCESSING
Granted: April 18, 2024
Application Number:
20240127414
Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure…
GRAPH NEURAL NETWORK MODEL FOR NEURAL NETWORK SCHEDULING DECISIONS
Granted: April 18, 2024
Application Number:
20240127031
A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the…
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Granted: April 18, 2024
Application Number:
20240126967
Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.
AUTOMATED DETECTION OF CASE-SPLITTING OPPORTUNITIES IN RTL
Granted: April 18, 2024
Application Number:
20240126964
Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware…
METHOD AND APPARATUS TO USE DRAM AS A CACHE FOR SLOW BYTE-ADDRESSIBLE MEMORY FOR EFFICIENT CLOUD APPLICATIONS
Granted: April 18, 2024
Application Number:
20240126695
Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be…
PREDICTIVE WORKLOAD ORCHESTRATION FOR DISTRIBUTED COMPUTING ENVIRONMENTS
Granted: April 18, 2024
Application Number:
20240126615
Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment…
PROGRAM ANALYSIS, DESIGN SPACE EXPLORATION AND VERIFICATION FOR HIGH-LEVEL SYNTHESIS VIA E-GRAPH REWRITING
Granted: April 18, 2024
Application Number:
20240126519
Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.
