FINE-GRAIN INTEGRATION OF RADIO FREQUENCY AND HIGH-VOLTAGE DEVICES
Granted: April 3, 2025
Application Number:
20250112216
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic…
MULTI-THRESHOLD SCHEME USING DUAL DIPOLE PATTERNING IN COMPLEMENTARY TRANSISTOR DIELECTRICS
Granted: April 3, 2025
Application Number:
20250113598
An integrated circuit (IC) device includes n- and p-type transistors with and without threshold voltage shifts using a common dopant material in a gate dielectric. The IC device includes at least four threshold voltage for each of n- and p-type transistors. Besides volumeless doping of gate dielectrics, work function metals are used in both n- and p-type transistors. A single dipole dopant may be concurrently introduced into and through similar gate dielectrics in both n- and p-type…
TRANSITION METAL DICHALCOGENIDE MONOLAYER TRANSFER USING LOW STRAIN TRANSFER PROTECTIVE LAYER
Granted: April 3, 2025
Application Number:
20250113573
A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate.…
EPI HEIGHT REDUCTION FOR IMPROVED TRANSISTOR PERFORMANCE
Granted: April 3, 2025
Application Number:
20250113564
An integrated circuit (IC) device has a stack of nanoribbons between epitaxial source and drain structures with first and second dielectric sections separated by a dielectric layer and adjacent an epitaxial structure. A second dielectric layer may separate a third dielectric section. The dielectric layers may be conformally between the epitaxial structure and the dielectric sections. A height at a top of the epitaxial structure may be reduced, for example, to be very close to a height at…
STACKED TRANSISTORS WITH STRAIN MATERIALS ON SOURCE AND DRAIN
Granted: April 3, 2025
Application Number:
20250113561
In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the…
DIRECT TRANSFER OF TRANSITION METAL DICHALCOGENIDE MONOLAYERS USING DIFFUSION BONDING LAYERS
Granted: April 3, 2025
Application Number:
20250113521
A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by…
METHODS AND APPARATUS TO SECURELY PERFORM CONFIGURATION UPDATES
Granted: April 3, 2025
Application Number:
20250112770
Disclosed examples generate an original equipment manufacturer (OEM) private key and an OEM public key; generate an OEM certificate based on the OEM public key; cause sending of the OEM certificate from an OEM product to a silicon provider, the silicon provider to sign the OEM certificate based on a silicon provider private key; and cause storage of the signed OEM certificate in the OEM product.
TECHNIQUES FOR USE OF MIXED WORD SIZE MULTIPLICATION FOR FULLY HOMOMORPHIC ENCRYPTION RELINEARIZATION
Granted: April 3, 2025
Application Number:
20250112757
Examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (FHE) workload. Examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.
SECURING AUDIO COMMUNICATIONS
Granted: April 3, 2025
Application Number:
20250112756
Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.
SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS
Granted: April 3, 2025
Application Number:
20250112218
In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the…
CROSS-LINKED HYDROPHOBIC COATING WITH PLASMA RESISTANCE FOR DIE-TO-WAFER SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250109221
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent…
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
Granted: April 3, 2025
Application Number:
20250112208
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
IN-CAVITY EPOXY PLACEMENT FOR PACKAGE RELIABILITY
Granted: April 3, 2025
Application Number:
20250112198
An apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. Other embodiments are also disclosed and claimed.
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
Granted: April 3, 2025
Application Number:
20250112196
An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112162
An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is…
TECHNOLOGIES FOR DIAMOND COMPOSITE MATERIALS MANUFACTURED VIA FIELD-ASSISTED SINTERING TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112112
Technologies for diamond composite materials are disclosed. In one embodiment, field-assisted sintering technology (FAST) is used to create a diamond composite material that includes diamond particles, copper, and chromium. The chromium can help bond the copper and the diamond particles. The diamond composite material has a high thermal conductivity, such as 500-1,000 W/(m·K). In one embodiment, the diamond composite material may be used in an integrated heat spreader in an integrated…
POOLED MEMORY ADDRESS TRANSLATION
Granted: April 3, 2025
Application Number:
20250110909
A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of…
PARTITIONED HOME SNOOP FILTER
Granted: April 3, 2025
Application Number:
20250110879
Techniques for partitioned home snoop filtering are described. In an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. The home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
DYNAMIC CACHE FILL PRIORIZATION
Granted: April 3, 2025
Application Number:
20250110876
Techniques for dynamic cache fill prioritization are described. In an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (MLC) unit including the cache, a local queue to store MLC lookup requests, an external queue to store MLC fill requests, and an MLC access control hardware. The MLC access control hardware is to dynamically switch prioritization of servicing the MLC lookup requests versus servicing the MLC fill requests.
METHODS AND APPARATUS TO REDUCE MEMORY POWER CONSUMPTION
Granted: April 3, 2025
Application Number:
20250110541
An example apparatus includes memory; machine-readable instructions; and at least one programmable circuit to at least one of execute or instantiate the machine-readable instructions to at least adjust a frequency of a clock signal of the memory based on workload demands of a processor circuit.
