MACHINE LEARNING SPARSE COMPUTATION MECHANISM
Granted: April 10, 2025
Application Number:
20250117873
Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
EXTENDED DRAIN TRANSISTOR FOR HIGH VOLTAGE APPLICATIONS
Granted: April 10, 2025
Application Number:
20250120143
Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in…
PACKAGE SUBSTRATES WITH COMPONENTS INCLUDED IN CAVITIES OF GLASS CORES
Granted: April 10, 2025
Application Number:
20250120102
Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.
RACKSIDE AUTOMATION FOR DATACENTER OPTIMIZATION
Granted: April 10, 2025
Application Number:
20250120036
A datacenter including a plurality of racks. The racks associated with a motorized and/or automated system to move the racks between first and second positions. In the first position, the racks are arranged in a side-by-side fashion in one or more rows. In the second position, a rack is moved so that a lateral side of the rack is accessible. In some embodiments, the racks include a motor and gear system for interacting with tracks. In some embodiments, each of the racks includes a…
HIGH THROUGHPUT CONTROL INFORMATION AND FIELD EXTENSION
Granted: April 10, 2025
Application Number:
20250119773
This disclosure describes systems, methods, and devices related to high throughput (HT) control information. A device may determine a frame comprising HT control information. The device may determine to extend a size of the HT control information. The device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (HT) control information, define a new control…
METHODS AND ARRANGEMENTS TO BOOST WIRELESS MEDIA QUALITY
Granted: April 10, 2025
Application Number:
20250119340
Logic may monitor quality of communication of data to a wireless receiver device based on transport characteristics at a wireless source device. Logic may evaluate the transport characteristics to identify indication(s) of a problem with the quality of the communication. Logic may identify a root cause associated with the indication(s). Logic may associate the root cause with one or more actions to mitigate the degradation of the quality. And logic may cause performance of an operation…
MICROELECTRONIC ASSEMBLIES INCLUDING SOLDER AND NON-SOLDER INTERCONNECTS
Granted: April 10, 2025
Application Number:
20250118698
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by…
PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS
Granted: April 10, 2025
Application Number:
20250118641
Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar,…
EXCEPTION HANDLING FOR DEBUGGING IN A GRAPHICS ENVIRONMENT
Granted: April 10, 2025
Application Number:
20250118003
An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory…
REDUCE POWER BY FRAME SKIPPING
Granted: April 10, 2025
Application Number:
20250117875
In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
MULTI-LAYERED OPTICAL INTEGRATED CIRCUIT ASSEMBLY WITH A MONOCRYSTALLINE WAVEGUIDE AND LOWER CRYSTALLINITY BONDING LAYER
Granted: April 10, 2025
Application Number:
20250116812
Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also…
HIGH AVAILABILITY AI VIA A PROGRAMMABLE NETWORK INTERFACE DEVICE
Granted: April 10, 2025
Application Number:
20250117673
Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate…
LOSS-ERROR-AWARE QUANTIZATION OF A LOW-BIT NEURAL NETWORK
Granted: April 10, 2025
Application Number:
20250117639
Methods, apparatus, systems and articles of manufacture for loss-error-aware quantization of a low-bit neural network are disclosed. An example apparatus includes a network weight partitioner to partition unquantized network weights of a first network model into a first group to be quantized and a second group to be retrained. The example apparatus includes a loss calculator to process network weights to calculate a first loss. The example apparatus includes a weight quantizer to…
UNCERTAINTY QUANTIFICATION FOR GENERATIVE ARTIFICIAL INTELLIGENCE MODEL
Granted: April 10, 2025
Application Number:
20250117633
Predictive uncertainty of a generative machine learning model may be estimated. The generative machine learning model may be a large language model or large multi-modal model. A datum may be input into the generative machine learning model. The generative machine learning model may generate outputs from the datum. Latent embeddings for the outputs may be extracted from the generative machine learning model. A covariance matrix with respect to the latent embeddings may be computed. The…
SYSTEM, METHOD AND APPARATUS FOR TOTAL STORAGE ENCRYPTION
Granted: April 10, 2025
Application Number:
20250117503
The disclosed embodiments are generally directed to inline encryption of data at line speed at a chip interposed between two memory components. The inline encryption may be implemented at a System-on-Chip (“SOC” or “SOC”). The memory components may comprise Non-Volatile Memory express (NVMe) and a dynamic random access memory (DRAM). An exemplary device includes an SOC to communicate with a Non-Volatile Memory NVMe circuitry to provide direct memory access (DMA) to an external…
TECHNOLOGIES FOR TRUSTED I/O PROTECTION OF I/O DATA WITH HEADER INFORMATION
Granted: April 10, 2025
Application Number:
20250117501
Technologies for trusted I/O include a computing device having a hardware cryptographic agent, a cryptographic engine, and an I/O controller. The hardware cryptographic agent intercepts a message from the I/O controller and identifies boundaries of the message. The message may include multiple DMA transactions, and the start of message is the start of the first DMA transaction. The cryptographic engine encrypts the message and stores the encrypted data in a memory buffer. The…
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
Granted: April 10, 2025
Application Number:
20250117360
A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the…
Instruction and Micro-Architecture Support for Decompression on Core
Granted: April 10, 2025
Application Number:
20250117329
Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of…
MEMORY RELIABILITY AVAILABILITY AND SERVICEABILITY (RAS) FOR WIRELESS NETWORKS
Granted: April 10, 2025
Application Number:
20250117318
Memory management for wireless networks is described. A method, includes accessing an operational parameter for a network slice of a wireless network, determining a first memory region of a plurality of memory regions in the memory pool based on the operational parameter, and encoding configuration information to allocate the first memory region to the network slice. Other embodiments are described and claimed.
PROCESSOR POWER MANAGEMENT
Granted: April 10, 2025
Application Number:
20250117060
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
