ENHANCED SIGNALING OF ADDITION AND DELETION OF COMMUNICATION LINKS FOR MULTI-LINK DEVICES
Granted: April 25, 2024
Application Number:
20240138006
This disclosure describes systems, methods, and devices related to adding or removing communication access points (APs) affiliated with an associated AP multi-link device (AP-MLD). A non-AP-MLD may identify a communication link between the non-AP-MLD and an AP-MLD, the communication link previously used by the non-AP-MLD; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-AP-MLD to transmit…
ENHANCED TRAFFIC INDICATIONS FOR MULTI-LINK WIRELESS COMMUNICATION DEVICES
Granted: April 25, 2024
Application Number:
20240137800
This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent…
IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS
Granted: April 25, 2024
Application Number:
20240136244
Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder…
DATA TRANSFER ENCRYPTION MECHANISM
Granted: April 25, 2024
Application Number:
20240134804
An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.
BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY
Granted: April 25, 2024
Application Number:
20240134797
Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a…
NAMED AND CLUSTER BARRIERS
Granted: April 25, 2024
Application Number:
20240134719
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier…
CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION
Granted: April 25, 2024
Application Number:
20240134603
The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the…
VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES
Granted: April 25, 2024
Application Number:
20240134527
Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message…
METHODS AND APPARATUS FOR DETECTING CARRIER TAPE HEIGHT LEVEL AND THICKNESS USING FIBER OPTIC SENSORS
Granted: April 25, 2024
Application Number:
20240133718
The disclosure is directed to apparatus and methods for detection of out of position (OOP) components in a carrier tape forming machine. An apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect OOP components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the OOP components on the carrier tape after overlaying with cover tape and prior to sealing and to detect…
Lossless Compression for Multisample Render Targets Alongside Fragment Compression
Granted: April 18, 2024
Application Number:
20240129503
Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing…
POWER OPTIMIZED BLEND
Granted: April 18, 2024
Application Number:
20240126357
Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.
METHOD AND SYSTEM OF VIDEO CODING WITH HANDLING OF ILLEGAL BLOCK PARTITIONS
Granted: April 18, 2024
Application Number:
20240129496
Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second…
ADAPTIVE DEFORMABLE KERNEL PREDICTION NETWORK FOR IMAGE DE-NOISING
Granted: April 18, 2024
Application Number:
20240127408
Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively…
GRAPH NEURAL NETWORK MODEL FOR NEURAL NETWORK SCHEDULING DECISIONS
Granted: April 18, 2024
Application Number:
20240127031
A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the…
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Granted: April 18, 2024
Application Number:
20240126967
Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.
AUTOMATED DETECTION OF CASE-SPLITTING OPPORTUNITIES IN RTL
Granted: April 18, 2024
Application Number:
20240126964
Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware…
METHOD AND APPARATUS TO USE DRAM AS A CACHE FOR SLOW BYTE-ADDRESSIBLE MEMORY FOR EFFICIENT CLOUD APPLICATIONS
Granted: April 18, 2024
Application Number:
20240126695
Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be…
CRYPTOGRAPHIC SEPARATION OF MMIO ON DEVICE
Granted: April 18, 2024
Application Number:
20240126691
Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely…
PREDICTIVE WORKLOAD ORCHESTRATION FOR DISTRIBUTED COMPUTING ENVIRONMENTS
Granted: April 18, 2024
Application Number:
20240126615
Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment…
PROGRAM ANALYSIS, DESIGN SPACE EXPLORATION AND VERIFICATION FOR HIGH-LEVEL SYNTHESIS VIA E-GRAPH REWRITING
Granted: April 18, 2024
Application Number:
20240126519
Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.
