ENHANCED SECURITY KEYS FOR WI-FI ASSOCIATION FRAMES
Granted: April 10, 2025
Application Number:
20250119733
This disclosure describes systems, methods, and devices related to using encrypted 802.11 association. A device may identify a beacon received from an access point (AP), the beacon including an indication of an authentication and key manager (AKM); transmit, to the AP, an 802.11 authentication request including an indication of parameters associated with the AKM; identify an 802.11 authentication response received from the AP based on the 802.11 authentication request, the 802.11…
REDUCE POWER BY FRAME SKIPPING
Granted: April 10, 2025
Application Number:
20250117875
In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
Granted: April 10, 2025
Application Number:
20250117873
Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
HIGH AVAILABILITY AI VIA A PROGRAMMABLE NETWORK INTERFACE DEVICE
Granted: April 10, 2025
Application Number:
20250117673
Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate…
LOSS-ERROR-AWARE QUANTIZATION OF A LOW-BIT NEURAL NETWORK
Granted: April 10, 2025
Application Number:
20250117639
Methods, apparatus, systems and articles of manufacture for loss-error-aware quantization of a low-bit neural network are disclosed. An example apparatus includes a network weight partitioner to partition unquantized network weights of a first network model into a first group to be quantized and a second group to be retrained. The example apparatus includes a loss calculator to process network weights to calculate a first loss. The example apparatus includes a weight quantizer to…
System, Apparatus And Method For Providing Protection Against Silent Data Corruption In A Link
Granted: April 10, 2025
Application Number:
20250117285
In one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (MAC) circuit coupled to the cryptographic circuit to compute a MAC comprising a tag using header information, the encrypted data, and the encrypted…
HIGH-PERFORMANCE INPUT-OUTPUT DEVICES SUPPORTING SCALABLE VIRTUALIZATION
Granted: April 10, 2025
Application Number:
20250117264
Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request…
DIE-TO-DIE INPUT/OUTPUT SIGNAL ROUTING UTILIZING OPPOSING DIE SURFACES IN INTEGRATED CIRCUIT COMPONENT PACKAGING
Granted: April 3, 2025
Application Number:
20250112205
Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid…
FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES
Granted: April 3, 2025
Application Number:
20250112210
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is…
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
Granted: April 3, 2025
Application Number:
20250112208
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER
Granted: April 3, 2025
Application Number:
20250108459
An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112204
An embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an L1 cache, an L2 cache, or both an L1 cache and an L2 cache, and wherein the first die or the second die is bonded to an adhesive area.
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112200
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
IN-CAVITY EPOXY PLACEMENT FOR PACKAGE RELIABILITY
Granted: April 3, 2025
Application Number:
20250112198
An apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. Other embodiments are also disclosed and claimed.
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
Granted: April 3, 2025
Application Number:
20250112196
An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
FINE-GRAIN INTEGRATION OF RADIO FREQUENCY ANTENNAS, INTERCONNECTS, AND PASSIVES
Granted: April 3, 2025
Application Number:
20250112188
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is…
IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT
Granted: April 3, 2025
Application Number:
20250112187
A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the…
BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASSISTED ASSEMBLY OF INTEGRATED CIRCUIT DIE STACKS
Granted: April 3, 2025
Application Number:
20250112181
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces…
REMOVAL OF DEFECTIVE DIES ON DONOR WAFERS FOR SELECTIVE LAYER TRANSFER
Granted: April 3, 2025
Application Number:
20250112067
In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a…
NEURAL INDIRECT ILLUMINATION WITH LIGHT METADATA ENCODING FOR DYNAMIC LIGHTING ENVIRONMENTS
Granted: April 3, 2025
Application Number:
20250111597
Described herein is a technique to approximate photorealistic indirect illumination shown in path traced images for dynamic lighting environments using a neural network. Given a lightly ray traced image, intermediate buffers from rendering pipeline, and light and camera information, the photorealism of rendered images can be enhanced via the neural network to approximate path traced indirect illumination.
