THROUGH-GLASS VIA LINERS FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: April 3, 2025
Application Number:
20250112163
An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged…
METHODS FOR DOPING 2D TRANSISTOR DEVICES AND RESULTING ARCHITECTURES
Granted: April 3, 2025
Application Number:
20250113599
Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.
STACKED TRANSISTORS WITH STRAIN MATERIALS ON SOURCE AND DRAIN
Granted: April 3, 2025
Application Number:
20250113561
In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the…
FOLDABLE THERMAL GROUND PLANES FOR ELECTRONIC DEVICES
Granted: April 3, 2025
Application Number:
20250113460
Systems, apparatus, articles of manufacture, and methods are disclosed for foldable thermal ground planes for electronic devices. An example an apparatus to cool an electronic device includes a first plate; a second plate; a plurality of first pillars extending between the first plate and the second plate, the plurality of first pillars having a first shape; a plurality of second pillars extending between the first plate and the second plate, the plurality of second pillars having a…
METHODS AND APPARATUS TO SECURELY PERFORM CONFIGURATION UPDATES
Granted: April 3, 2025
Application Number:
20250112770
Disclosed examples generate an original equipment manufacturer (OEM) private key and an OEM public key; generate an OEM certificate based on the OEM public key; cause sending of the OEM certificate from an OEM product to a silicon provider, the silicon provider to sign the OEM certificate based on a silicon provider private key; and cause storage of the signed OEM certificate in the OEM product.
FINE-GRAIN INTEGRATION OF RADIO FREQUENCY AND HIGH-VOLTAGE DEVICES
Granted: April 3, 2025
Application Number:
20250112216
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic…
FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES
Granted: April 3, 2025
Application Number:
20250112210
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is…
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
Granted: April 3, 2025
Application Number:
20250112208
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112204
An embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an L1 cache, an L2 cache, or both an L1 cache and an L2 cache, and wherein the first die or the second die is bonded to an adhesive area.
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
Granted: April 3, 2025
Application Number:
20250112196
An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
ARCHITECTURES AND METHODS FOR ATTACHING PHOTONIC INTEGRATED CIRCUITS (PICs) TO OPTICAL CONNECTORS
Granted: April 3, 2025
Application Number:
20250110285
Architectures and methods for attaching photonic integrated circuits (PICs) to optical connectors. The architectures are characterized by (1) a cavity at a specific location with respect to a trench alongside an optical facet of the PIC die, (2) index matching epoxy (IME) in the trench and in the cavity, and (3) the use of a snap cure adhesive between the PIC and the optical connector.
MAGNETIC AND ELECTRIC STRUCTURES IN TECHNOLOGIES WITH THROUGH-SILICON VIAS AND FRONT- AND BACK-END METAL LAYERS
Granted: April 3, 2025
Application Number:
20250112147
An integrated circuit device with front- and back-side metals may include coils in interconnect structures on one or both sides of a semiconductor substrate. The coil(s) may include vias extending through (and coupling wires on both sides of) the substrate. The coil(s) may include multiple turns or loops. The coil(s) may be on one side, and parallel to, the substrate. Coils may be orthogonal or parallel to each other. A resistor may have smaller resistor segments on both sides of the…
BACKSIDE POWER GATING
Granted: April 3, 2025
Application Number:
20250112122
Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
FLEXIBLE THERMAL INTERPOSER FOR BACKSIDE COOLING OF DOUBLE-SIDED PACKAGES
Granted: April 3, 2025
Application Number:
20250112106
An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally…
APPARATUS AND METHODS FOR CAPILLARY UNDERFILL OF EMBEDDED DEVICES
Granted: April 3, 2025
Application Number:
20250112085
An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface…
HARDWARE ACCELERATION OF DICTIONARY COMPRESSION
Granted: April 3, 2025
Application Number:
20250110903
A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.
PARTITIONED HOME SNOOP FILTER
Granted: April 3, 2025
Application Number:
20250110879
Techniques for partitioned home snoop filtering are described. In an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. The home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
DEVICE, METHOD AND SYSTEM FOR COMMUNICATING BETWEEN NETWORKED AGENTS VIA A CREDIT MANAGEMENT BUS
Granted: April 3, 2025
Application Number:
20250110813
Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the…
CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT FLOATING POINT FORMAT IN A GRAPHICS ARCHITECTURE
Granted: April 3, 2025
Application Number:
20250110733
An apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. The apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide…
OPTICAL CONNECTOR FERRULE
Granted: April 3, 2025
Application Number:
20250110289
A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more…
