DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112124
DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and…
METHODS FOR DOPING 2D TRANSISTOR DEVICES AND RESULTING ARCHITECTURES
Granted: April 3, 2025
Application Number:
20250113599
Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.
SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID BONDED DIE STACKS
Granted: April 3, 2025
Application Number:
20250112177
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed…
MICROELECTRONIC ASSEMBLIES WITH EDGE STRESS REDUCTION IN GLASS CORES
Granted: April 3, 2025
Application Number:
20250112175
Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a…
PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES
Granted: April 3, 2025
Application Number:
20250112173
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
HYBRID BONDING WITH EMBEDDED ALIGNMENT MARKERS
Granted: April 3, 2025
Application Number:
20250112168
Alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. The alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. A reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. The alignment markers can further be used to…
THROUGH-GLASS VIA LINERS FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: April 3, 2025
Application Number:
20250112163
An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged…
DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112162
An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is…
MICROELECTRONIC STRUCTURES INCLUDING GLASS SUBSTRATES WITH DIELECTRIC BASED LINER MATERIALS.
Granted: April 3, 2025
Application Number:
20250112138
Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.
IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES
Granted: April 3, 2025
Application Number:
20250112127
A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding…
PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER
Granted: April 3, 2025
Application Number:
20250108459
An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.
NEURAL INDIRECT ILLUMINATION WITH LIGHT METADATA ENCODING FOR DYNAMIC LIGHTING ENVIRONMENTS
Granted: April 3, 2025
Application Number:
20250111597
Described herein is a technique to approximate photorealistic indirect illumination shown in path traced images for dynamic lighting environments using a neural network. Given a lightly ray traced image, intermediate buffers from rendering pipeline, and light and camera information, the photorealism of rendered images can be enhanced via the neural network to approximate path traced indirect illumination.
POOLED MEMORY ADDRESS TRANSLATION
Granted: April 3, 2025
Application Number:
20250110909
A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of…
HARDWARE ACCELERATION OF DICTIONARY COMPRESSION
Granted: April 3, 2025
Application Number:
20250110903
A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.
PARTITIONED HOME SNOOP FILTER
Granted: April 3, 2025
Application Number:
20250110879
Techniques for partitioned home snoop filtering are described. In an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. The home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND STOCHASTIC ROUNDING OPERATIONS IN A GRAPHICS ARCHITECTURE
Granted: April 3, 2025
Application Number:
20250110741
An apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded…
CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT FLOATING POINT FORMAT IN A GRAPHICS ARCHITECTURE
Granted: April 3, 2025
Application Number:
20250110733
An apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. The apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide…
TECHNOLOGIES FOR THERMAL PLUGS IN A PHOTONIC INTEGRATED CIRCUIT DIE
Granted: April 3, 2025
Application Number:
20250110301
Technologies for thermal plugs in photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, several thermal plugs extend from contact pads in a PIC die, through a dielectric layer, to a waveguide layer. The thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the PIC die. The PIC die may be mounted on an electronic integrated circuit (EIC) die in an integrated circuit component. The PIC die…
OPTICAL CO-PACKAGING ON A GLASS SUBSTRATE WITH 3D DIE-STACKING
Granted: April 3, 2025
Application Number:
20250110270
The substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. The multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (PIC) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second PIC die. The integrated circuit…
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: April 3, 2025
Application Number:
20250110209
For example, a radar Radio Head (RH) may be configured to determine Range-Doppler (RD) information corresponding to a plurality of RD bins based on digital radar Receive (Rx) signals representing radar Radio Frequency (RF) Rx signals received by one or more Rx antennas; to detect one or more detected RD bins based on the RD information; to provide filtered RD information including RD information corresponding to the one or more detected RD bins and excluding RD information of one or more…
