STACKED TRANSISTORS WITH STRAIN MATERIALS ON SOURCE AND DRAIN
Granted: April 3, 2025
Application Number:
20250113561
In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the…
DIRECT TRANSFER OF TRANSITION METAL DICHALCOGENIDE MONOLAYERS USING DIFFUSION BONDING LAYERS
Granted: April 3, 2025
Application Number:
20250113521
A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by…
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
Granted: April 3, 2025
Application Number:
20250112196
An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
SELF-DIFFUSING LIQUID METAL INTERCONNECT ARCHITECTURES ENABLING SNAP-ON ROOM TEMPERATURE ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112190
In one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. The substrate includes first reservoirs comprising Gallium-based liquid metal (LM), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. The component includes circuitry and conductive contacts connected to the circuitry. Each contact defines a cavity and a portion of each conductive…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL ISOMERIC MOIETIES AND NON-THERMAL ISOMERIC MOIETIES
Granted: April 3, 2025
Application Number:
20250112144
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy…
DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
Granted: March 27, 2025
Application Number:
20250107156
Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
INTEGRATED CIRCUIT DEVICES WITH REPLICA CELLS AND FILLER CELLS FOR REDUCING LOCAL LAYOUT EFFECTS
Granted: March 27, 2025
Application Number:
20250107243
An IC device may include functional regions as well as replica cells and filler cells that can reduce local layout effect in the IC device. A functional region includes functional cells, e.g., logic cell or memory cells. A white space may be between a first functional region and a second functional region. A first portion of the white space may be filled with replica cells, each of which is a replica of a cell in the first functional region. A second portion of the white space may be…
QUANTUM DOT DEVICES
Granted: March 27, 2025
Application Number:
20250107221
Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second…
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
Granted: March 27, 2025
Application Number:
20250107212
Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
MATERIAL LAYER CONTAINING MOLYBDENUM TO PROTECT GATE DIELECTRIC
Granted: March 27, 2025
Application Number:
20250107209
Techniques are provided to form an integrated circuit having a gate electrode that includes at least one layer containing molybdenum. A transistor includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets) of semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric with at least one of those conductive layers containing molybdenum…
INTEGRATED CIRCUIT DEVICES WITH VIAS HAVING WIDENED ENDS FOR POWER DELIVERY
Granted: March 27, 2025
Application Number:
20250105095
An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between…
ARCHITECTURES AND METHODS TO MODULATE CONTACT RESISTANCE IN 2D MATERIALS FOR USE IN FIELD EFFECT TRANSISTOR DEVICES
Granted: March 27, 2025
Application Number:
20250107147
Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
Granted: March 27, 2025
Application Number:
20250107108
An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells.…
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
Granted: March 27, 2025
Application Number:
20250107107
An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers.…
TIME RECOVERY FROM ATTACKS ON DELAYED AUTHENTICATION
Granted: March 27, 2025
Application Number:
20250106207
Techniques to perform time recovery from attacks on delayed authentication in a time synchronized network are described. One embodiment comprises a method for decoding time information and a message authentication code (MAC) from a time message, the time information to synchronize a local clock for a device to a network time of a time synchronized network (TSN), and the MAC to authenticate the time message, determining whether the time message is authentic using the MAC, discarding the…
TECHNOLOGIES FOR PROVIDING SECURE UTILIZATION OF TENANT KEYS
Granted: March 27, 2025
Application Number:
20250106191
Technologies for providing secure utilization of tenant keys include a compute device. The compute device includes circuitry configured to obtain a tenant key. The circuitry is also configured to receive encrypted data associated with a tenant. The encrypted data defines an encrypted image that is executable by the compute device to perform a workload on behalf of the tenant in a virtualized environment. Further, the circuitry is configured to utilize the tenant key to decrypt the…
METHODS AND ARRANGEMENTS FOR AN N-PATH FILTER USING A FOURTH ORDER ALL POLE DRIVING POINT IMPEDANCE
Granted: March 27, 2025
Application Number:
20250105860
Embodiments may comprise N-path filter circuitry with tunable radio frequency selectivity and up to 80 decibels per decade roll-off. The N-path filter may comprise at least one input transistor, wherein the at least one input transistor comprises a channel and a gate. A first end of the channel is coupled with a receiver circuitry input, wherein a second end of the channel is coupled with a load. The gate of the at least one input transistor is coupled with a clock circuitry input. The…
Techniques For Output Control During Update Of An Integrated Circuit
Granted: March 27, 2025
Application Number:
20250105847
An integrated circuit includes an update controller circuit, updatable logic circuits, and an output circuit. The update controller circuit is configured to control an output signal of the output circuit that is provided to an external conductor during reconfiguration of the updatable logic circuits.
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE LAST APPROACH
Granted: March 27, 2025
Application Number:
20250105222
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE COUPLED TO A GLASS CORE BY INTERCONNECTS
Granted: March 27, 2025
Application Number:
20250105156
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual…
