CONFORMAL COATINGS WITH SPATIALLY DEFINED SURFACE ENERGIES FOR DIE-TO-WAFER SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112155
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior…
TRANSITION METAL DICHALCOGENIDE MONOLAYER TRANSFER USING LOW STRAIN TRANSFER PROTECTIVE LAYER
Granted: April 3, 2025
Application Number:
20250113573
A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate.…
METHOD OF FABRICATING A 2D CHANNEL TRANSISTOR BY EMPLOYING SELECTIVE METALLIZATION TO FORM A SOURCE OR DRAIN STRUCTURE
Granted: April 3, 2025
Application Number:
20250113572
Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to…
SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS
Granted: April 3, 2025
Application Number:
20250112218
In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the…
SELECTIVE LAYER TRANSFER WITH GLASS PANELS
Granted: April 3, 2025
Application Number:
20250112208
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112204
An embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an L1 cache, an L2 cache, or both an L1 cache and an L2 cache, and wherein the first die or the second die is bonded to an adhesive area.
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112200
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES
Granted: April 3, 2025
Application Number:
20250112196
An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES
Granted: April 3, 2025
Application Number:
20250112173
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
THROUGH-GLASS VIA LINERS FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: April 3, 2025
Application Number:
20250112163
An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged…
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: April 3, 2025
Application Number:
20250110209
For example, a radar Radio Head (RH) may be configured to determine Range-Doppler (RD) information corresponding to a plurality of RD bins based on digital radar Receive (Rx) signals representing radar Radio Frequency (RF) Rx signals received by one or more Rx antennas; to detect one or more detected RD bins based on the RD information; to provide filtered RD information including RD information corresponding to the one or more detected RD bins and excluding RD information of one or more…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL ISOMERIC MOIETIES AND NON-THERMAL ISOMERIC MOIETIES
Granted: April 3, 2025
Application Number:
20250112144
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy…
MICROELECTRONIC STRUCTURES INCLUDING GLASS SUBSTRATES WITH DIELECTRIC BASED LINER MATERIALS.
Granted: April 3, 2025
Application Number:
20250112138
Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.
HARDWARE ACCELERATION OF DICTIONARY COMPRESSION
Granted: April 3, 2025
Application Number:
20250110903
A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.
DYNAMIC CACHE FILL PRIORIZATION
Granted: April 3, 2025
Application Number:
20250110876
Techniques for dynamic cache fill prioritization are described. In an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (MLC) unit including the cache, a local queue to store MLC lookup requests, an external queue to store MLC fill requests, and an MLC access control hardware. The MLC access control hardware is to dynamically switch prioritization of servicing the MLC lookup requests versus servicing the MLC fill requests.
SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND STOCHASTIC ROUNDING OPERATIONS IN A GRAPHICS ARCHITECTURE
Granted: April 3, 2025
Application Number:
20250110741
An apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded…
INSTRUCTION BLOCK BASED PERFORMANCE MONITORING
Granted: April 3, 2025
Application Number:
20250110739
Techniques for block based performance monitoring are described. In an embodiment, an apparatus includes execution hardware to execute a plurality of instructions; and block-based sampling hardware. The block-based sampling hardware is to identify, based on a first branch instruction of the plurality of instructions and a second branch instruction of the plurality of instructions, a block of instructions; and to collect, during execution of the block of instructions, performance…
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS
Granted: April 3, 2025
Application Number:
20250110737
An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf…
TECHNOLOGIES FOR AN OPTICAL INTERPOSER WITH ACTUATOR BEAMS
Granted: April 3, 2025
Application Number:
20250110294
Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator…
ARCHITECTURES AND METHODS FOR ATTACHING PHOTONIC INTEGRATED CIRCUITS (PICs) TO OPTICAL CONNECTORS
Granted: April 3, 2025
Application Number:
20250110285
Architectures and methods for attaching photonic integrated circuits (PICs) to optical connectors. The architectures are characterized by (1) a cavity at a specific location with respect to a trench alongside an optical facet of the PIC die, (2) index matching epoxy (IME) in the trench and in the cavity, and (3) the use of a snap cure adhesive between the PIC and the optical connector.
