INTEGRATED CIRCUIT DEVICES WITH VIAS HAVING WIDENED ENDS FOR POWER DELIVERY
Granted: March 27, 2025
Application Number:
20250105095
An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between…
QUANTUM DOT DEVICES
Granted: March 27, 2025
Application Number:
20250107221
Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second…
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
Granted: March 27, 2025
Application Number:
20250107212
Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
Granted: March 27, 2025
Application Number:
20250107108
An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells.…
TIME RECOVERY FROM ATTACKS ON DELAYED AUTHENTICATION
Granted: March 27, 2025
Application Number:
20250106207
Techniques to perform time recovery from attacks on delayed authentication in a time synchronized network are described. One embodiment comprises a method for decoding time information and a message authentication code (MAC) from a time message, the time information to synchronize a local clock for a device to a network time of a time synchronized network (TSN), and the MAC to authenticate the time message, determining whether the time message is authentic using the MAC, discarding the…
TECHNOLOGIES FOR PROVIDING SECURE UTILIZATION OF TENANT KEYS
Granted: March 27, 2025
Application Number:
20250106191
Technologies for providing secure utilization of tenant keys include a compute device. The compute device includes circuitry configured to obtain a tenant key. The circuitry is also configured to receive encrypted data associated with a tenant. The encrypted data defines an encrypted image that is executable by the compute device to perform a workload on behalf of the tenant in a virtualized environment. Further, the circuitry is configured to utilize the tenant key to decrypt the…
METHODS AND ARRANGEMENTS FOR AN N-PATH FILTER USING A FOURTH ORDER ALL POLE DRIVING POINT IMPEDANCE
Granted: March 27, 2025
Application Number:
20250105860
Embodiments may comprise N-path filter circuitry with tunable radio frequency selectivity and up to 80 decibels per decade roll-off. The N-path filter may comprise at least one input transistor, wherein the at least one input transistor comprises a channel and a gate. A first end of the channel is coupled with a receiver circuitry input, wherein a second end of the channel is coupled with a load. The gate of the at least one input transistor is coupled with a clock circuitry input. The…
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE LAST APPROACH
Granted: March 27, 2025
Application Number:
20250105222
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having…
HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE FIRST APPROACH
Granted: March 27, 2025
Application Number:
20250105209
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE COUPLED TO A GLASS CORE BY INTERCONNECTS
Granted: March 27, 2025
Application Number:
20250105156
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual…
TECHNOLOGIES FOR DUAL TUNABLE LASERS IN A PHOTONIC INTEGRATED CIRCUIT DIE
Granted: March 27, 2025
Application Number:
20250102634
Technologies for tunable lasers in a photonic integrated circuit (PIC) die are disclosed. In an illustrative embodiment, a lidar system includes a PIC die with two lasers. The PIC die includes a switch to switch between the output of the first laser and the output of the second laser. Each laser can be tuned to different peaks of a Bragg grating in the cavity of the laser, and each laser can be frequency swept within the peak of the Bragg grating. In operation, one laser is changed to a…
GLASS CORES INCLUDING PROTRUDING THROUGH GLASS VIAS AND RELATED METHODS
Granted: March 27, 2025
Application Number:
20250105074
Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
SELECTIVE LAYER TRANSFER
Granted: March 27, 2025
Application Number:
20250105046
Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second…
MEMORY ISOLATION TO IMPROVE SYSTEM RELIABILITY
Granted: March 27, 2025
Application Number:
20250104797
Example systems, apparatus, articles of manufacture, and methods that perform memory preservation to improve system reliability are disclosed. Example apparatus disclosed herein increment an error count after detection of an error associated with a memory cell. Example apparatus also isolate a system memory address of the memory cell based on the error count.
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
Granted: March 27, 2025
Application Number:
20250104760
An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled…
Current Control Systems And Methods For Communications Between Devices
Granted: March 27, 2025
Application Number:
20250104745
An integrated circuit includes a communication controller circuit for exchanging communications with a device external to the integrated circuit through a signal line, a current circuit coupled to the signal line, and a current controller circuit for causing the current circuit to provide a constant current to the signal line while a signal is transmitted through the signal line based on a command generated by the communication controller circuit.
PROGRESSIVE MULTISAMPLE ANTI-ALIASING
Granted: March 27, 2025
Application Number:
20250104326
One embodiment provides a graphics processor comprising an interface to a system interconnect and a graphics processor coupled to the interface, the graphics processor comprising circuitry configured to compact sample data for multiple sample locations of a pixel, map the multiple sample locations to memory locations that store compacted sample data, the memory locations in a memory of the graphics processor, apply lossless compression to the compacted sample data, and update a…
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
Granted: March 27, 2025
Application Number:
20250104179
A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with…
CACHE STRUCTURE AND UTILIZATION
Granted: March 27, 2025
Application Number:
20250103546
Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache,…
QUALITY OF SERVICE SUPPORT FOR INPUT/OUTPUT AND OTHER AGENTS
Granted: March 27, 2025
Application Number:
20250103397
Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more…
