AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
Granted: March 27, 2025
Application Number:
20250107212
Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure…
SELECTIVE TRANSFER OF OPTICAL AND OPTO-ELECTRONIC COMPONENTS
Granted: March 27, 2025
Application Number:
20250105053
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or…
Current Control Systems And Methods For Communications Between Devices
Granted: March 27, 2025
Application Number:
20250104745
An integrated circuit includes a communication controller circuit for exchanging communications with a device external to the integrated circuit through a signal line, a current circuit coupled to the signal line, and a current controller circuit for causing the current circuit to provide a constant current to the signal line while a signal is transmitted through the signal line based on a command generated by the communication controller circuit.
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
Granted: March 27, 2025
Application Number:
20250104180
Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
ROBUST WAVEGUIDE ALIGNMENT MECHANISM
Granted: March 27, 2025
Application Number:
20250102745
In one embodiment, a device includes a fiber array unit (FAU) coupled to a photonics integrated circuit (PIC) die. The PIC die includes a cavity defined at an edge of the PIC die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. The PIC die further includes first waveguides protruding into the cavity of the PIC die. The FAU includes a shelf portion extending from a body portion, and a plurality of second…
MICROELECTRONIC ASSEMBLY WITH BRIDGE DIE AND SELECTIVE METALLIZATION LAYERS
Granted: March 20, 2025
Application Number:
20250096143
A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped…
METHODS AND APPARATUS FOR ARTIFICIAL INTELLIGENCE (AI) MODEL SECURITY PROTECTION USING MOVING TARGET DEFENSES
Granted: March 20, 2025
Application Number:
20250097249
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in…
TECHNIQUES FOR ARTIFICIAL INTELLIGENCE CAPABILITIES AT A NETWORK SWITCH
Granted: March 20, 2025
Application Number:
20250097120
Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.
MICROELECTRONIC ASSEMBLIES
Granted: March 20, 2025
Application Number:
20250096194
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts…
MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)
Granted: March 20, 2025
Application Number:
20250096178
Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal…
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: March 20, 2025
Application Number:
20250093498
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, a radar system may include a plurality of radar devices. For example, a radar device may include one or more Transmit (Tx) antennas to transmit radar Tx signals, one or more Receive (Rx) antennas to receive radar Rx signals, and a processor to generate radar information based on the radar Rx signals. In one example, the radar system may be implemented as part of a vehicle. In other…
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
Granted: March 20, 2025
Application Number:
20250096114
Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure…
MICROELECTRONIC ASSEMBLIES HAVING A BRIDGE DIE OVER A GLASS PATCH
Granted: March 20, 2025
Application Number:
20250096053
A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an…
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
Granted: March 20, 2025
Application Number:
20250095693
An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit…
LOW RANK MATRIX COMPRESSION
Granted: March 20, 2025
Application Number:
20250095217
In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.
DISTORTION MESHES AGAINST CHROMATIC ABERRATIONS
Granted: March 20, 2025
Application Number:
20250095122
Described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. The plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. The plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic…
PAGE FAULTING AND SELECTIVE PREEMPTION
Granted: March 20, 2025
Application Number:
20250095099
One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at…
MULTI-GRANULAR CLUSTERING-BASED SOLUTION FOR KEY-VALUE CACHE COMPRESSION
Granted: March 20, 2025
Application Number:
20250094712
Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, a multi-granular clustering-based solution for KV cache compression can be implemented. Key tensors and value tensors corresponding unimportant tokens can…
EFFICIENT SECURITY METADATA ENCODING IN ERROR CORRECTING CODE (ECC) MEMORY WITHOUT DEDICATED ECC BITS
Granted: March 20, 2025
Application Number:
20250094275
The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store…
INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING
Granted: March 20, 2025
Application Number:
20250094170
One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein…
