DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112162
An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is…
TRANSITION METAL DICHALCOGENIDE MONOLAYER TRANSFER USING LOW STRAIN TRANSFER PROTECTIVE LAYER
Granted: April 3, 2025
Application Number:
20250113573
A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate.…
METHOD OF FABRICATING A 2D CHANNEL TRANSISTOR BY EMPLOYING SELECTIVE METALLIZATION TO FORM A SOURCE OR DRAIN STRUCTURE
Granted: April 3, 2025
Application Number:
20250113572
Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to…
TECHNOLOGIES FOR REDUCING THE IMPACT OF RADIOFREQUENCY INTERFERENCE ON A CIRCUIT BOARD
Granted: April 3, 2025
Application Number:
20250113430
Technologies for reducing the impact of inductors on electrical traces are disclosed. In an illustrative embodiment, conductive ink is applied in a silk screen layer on top of a solder mask of a circuit board. The conductive ink forms shield regions under and near where inductors are placed and/or where a power plane is routed. The conductive shield regions may be coupled to a ground plane in the circuit board. The conductive shield regions can partially shield traces under and near the…
FINE-GRAIN INTEGRATION OF RADIO FREQUENCY AND HIGH-VOLTAGE DEVICES
Granted: April 3, 2025
Application Number:
20250112216
Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic…
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112200
A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In…
IN-CAVITY EPOXY PLACEMENT FOR PACKAGE RELIABILITY
Granted: April 3, 2025
Application Number:
20250112198
An apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. Other embodiments are also disclosed and claimed.
SUPERHYDROPHOBIC SURFACES FOR LIQUID CONTAINMENT IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF INTEGRATED CIRCUIT DIE STACKS
Granted: April 3, 2025
Application Number:
20250112185
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid…
BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASSISTED ASSEMBLY OF INTEGRATED CIRCUIT DIE STACKS
Granted: April 3, 2025
Application Number:
20250112181
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces…
MICROELECTRONIC ASSEMBLIES WITH EDGE STRESS REDUCTION IN GLASS CORES
Granted: April 3, 2025
Application Number:
20250112175
Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a…
OPTICAL CO-PACKAGING ON A GLASS SUBSTRATE WITH 3D DIE-STACKING
Granted: April 3, 2025
Application Number:
20250110270
The substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. The multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (PIC) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second PIC die. The integrated circuit…
IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES
Granted: April 3, 2025
Application Number:
20250112127
A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding…
BACKSIDE POWER GATING
Granted: April 3, 2025
Application Number:
20250112122
Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
TECHNOLOGIES FOR DIAMOND COMPOSITE MATERIALS MANUFACTURED VIA FIELD-ASSISTED SINTERING TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112112
Technologies for diamond composite materials are disclosed. In one embodiment, field-assisted sintering technology (FAST) is used to create a diamond composite material that includes diamond particles, copper, and chromium. The chromium can help bond the copper and the diamond particles. The diamond composite material has a high thermal conductivity, such as 500-1,000 W/(m·K). In one embodiment, the diamond composite material may be used in an integrated heat spreader in an integrated…
DIE EMBEDDED IN GLASS LAYER WITH TWO-SIDE CONNECTIVITY
Granted: April 3, 2025
Application Number:
20250112100
An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to…
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS
Granted: April 3, 2025
Application Number:
20250112077
An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.
PARTITIONED HOME SNOOP FILTER
Granted: April 3, 2025
Application Number:
20250110879
Techniques for partitioned home snoop filtering are described. In an embodiment, an apparatus includes multiple caching agent circuits and a home agent circuit. The home agent circuit controls cache coherency using a snoop filter including multiple partitions, each corresponding to a corresponding one of the caching agent circuits.
TECHNOLOGIES FOR THERMAL PLUGS IN A PHOTONIC INTEGRATED CIRCUIT DIE
Granted: April 3, 2025
Application Number:
20250110301
Technologies for thermal plugs in photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, several thermal plugs extend from contact pads in a PIC die, through a dielectric layer, to a waveguide layer. The thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the PIC die. The PIC die may be mounted on an electronic integrated circuit (EIC) die in an integrated circuit component. The PIC die…
POLYETHYLENE OXIDE-BASED OPTICAL ADHESIVE
Granted: April 3, 2025
Application Number:
20250110295
A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
TECHNOLOGIES FOR AN OPTICAL INTERPOSER WITH ACTUATOR BEAMS
Granted: April 3, 2025
Application Number:
20250110294
Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator…
