Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
Granted: March 4, 2025
Patent Number:
12243812
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and…
Reinforcement learning (RL) and graph neural network (GNN)-based resource management for wireless access networks
Granted: March 4, 2025
Patent Number:
12245052
A computing node to implement an RL management entity in an NG wireless network includes a NIC and processing circuitry coupled to the NIC. The processing circuitry is configured to generate a plurality of network measurements for a corresponding plurality of network functions. The functions are configured as a plurality of ML models forming a multi-level hierarchy. Control signaling from an ML model of the plurality is decoded, the ML model being at a predetermined level (e.g., a lowest…
Determining adaptive quantization matrices using machine learning for video coding
Granted: March 4, 2025
Patent Number:
12244807
Techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. Such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.
Methods and apparatus to perform dirty region reads and writes to reduce memory bandwidth usage
Granted: March 4, 2025
Patent Number:
12244798
An example apparatus includes image processing circuitry to determine an uncovered region of a background image in a current video frame relative to the background image in a previous video frame, the uncovered region obscured in the previous video frame by a first foreground region of the previous video frame, and the uncovered region uncovered in the current video frame based on movement of a second foreground region in the current video frame relative to the first foreground region of…
Intelligent data forwarding in edge networks
Granted: March 4, 2025
Patent Number:
12244507
Systems and techniques for intelligent data forwarding in edge networks are described herein. A request may be received from an edge user device for a service via a first endpoint. A time value may be calculated using a timestamp of the request. Motion characteristics may be determined for the edge user device using the time value. A response to the request may be transmitted to a second endpoint based on the motion characteristics.
Encoder and decoder of forward error correction (FEC) codec
Granted: March 4, 2025
Patent Number:
12244326
A FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input byte of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a…
Forksheet transistors with dielectric or conductive spine
Granted: March 4, 2025
Patent Number:
12243875
Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure…
Fan out packaging pop mechanical attach method
Granted: March 4, 2025
Patent Number:
12243856
Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of…
Microelectronic assemblies having topside power delivery structures
Granted: March 4, 2025
Patent Number:
12243828
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the…
Hybrid conductive vias for electronic substrates
Granted: March 4, 2025
Patent Number:
12243825
An electronic substrate may be fabricated to include a fine pitch dielectric layer having an upper surface, a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer, and at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer. The hybrid conductive via is fabricated such that a portion thereof that extends through the fine pitch dielectric layer is smaller than a portion extending through…
Electronic device
Granted: March 4, 2025
Patent Number:
D1065180
Nested architectures for enhanced heterogeneous integration
Granted: March 4, 2025
Patent Number:
12243806
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first…
Microelectronic structures including bridges
Granted: March 4, 2025
Patent Number:
12243792
Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
Cooperative adaptive cruise control (CACC) system for control of connected and autonomous vehicle (CAV) platoons
Granted: March 4, 2025
Patent Number:
12243429
Techniques are disclosed to increase the safety of vehicles travelling in a vehicle platoon. These techniques include the utilization of a comprehensive safety framework such as a safety driving model (SDM) for the platoon control systems. In contrast to the conventional approaches, the use of the SDM model allows for platoon vehicle control systems to consider the acceleration/deceleration capabilities of the vehicles to calculate minimum safe longitudinal distances between the platoon…
Video smoothing mechanism
Granted: March 4, 2025
Patent Number:
12243192
An apparatus to facilitate video motion smoothing is disclosed. The apparatus comprises one or more processors including a graphics processor, the one or more processors including circuitry configured to receive a video stream, decode the video stream to generate a motion vector map and a plurality of video image frames, analyze the motion vector map to detect a plurality of candidate frames, wherein the plurality of candidate frames comprise a period of discontinuous motion in the…
Methods and arrangements for a personal point of sale device
Granted: March 4, 2025
Patent Number:
12243037
Logic to register a personal point of sale (POS) device. Logic may communicate with the registration processor to establish a secure communication channel. Logic may access a basic input output system to obtain platform information. Logic may transmit the platform information to the registration processor to identify a certification associated with the device. Logic may communicate with a payment instrument via a card reader. Logic may transmit an encrypted message from the card reader…
Methods and apparatus to optimize workflows
Granted: March 4, 2025
Patent Number:
12242889
Methods, apparatus, systems and articles of manufacture are disclosed that optimize workflows. An example apparatus includes an intent determiner to determine an objective of a user input, the objective indicating a task to be executed in an infrastructure, a configuration composer to compose a plurality of workflows based on the determined objective, a model executor to execute a machine learning model to create a confidence score relating to the plurality of workflows, and a workflow…
Multi-protocol support on common physical layer
Granted: March 4, 2025
Patent Number:
12242336
Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a…
Power supply optimization based on interface card power enable signaling
Granted: March 4, 2025
Patent Number:
12242319
An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is…
Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures
Granted: March 4, 2025
Patent Number:
12242290
In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive…
