Technologies for expanded trusted domains
Granted: March 18, 2025
Patent Number:
12254337
Techniques for expanded trusted domains are disclosed. In the illustrative embodiment, a trusted domain can be established that includes hardware components from a processor as well as an off-load device. The off-load device may provide compute resources for the trusted domain. The trusted domain can be expanded and contracted on-demand, allowing for a flexible approach to creating and using trusted domains.
Hybrid boards with embedded planes
Granted: March 18, 2025
Patent Number:
12256487
The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a…
Systems and methods for module configurability
Granted: March 18, 2025
Patent Number:
12256467
A component (e.g. a module configuration system) of a device may include an interface and processor circuitry. The processor circuitry may be configured to: determine identification information of a hardware device (e.g. module, microchip) connected to the component via the interface; obtain device information for the connected hardware device based on the determined identification information; and initialize the connected hardware device based on the obtained device information.
Separate network slicing for security events propagation across layers on special packet data protocol context
Granted: March 18, 2025
Patent Number:
12256218
An apparatus and system to provide separate network slices for security events are described. A dedicated secure network slice is provided for PDP data from a UE. The network slice is used for detecting security issues and sending security-related information to clients. The communications in the dedicated network slice are associated with a special PDP context used by the UE to interface with the network slice. Once the UE has detected a security issue or has been notified of the…
Multi-deck non-volatile memory architecture with reduced termination tile area
Granted: March 18, 2025
Patent Number:
12254946
In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set…
Smart prologue for nonvolatile memory program operation
Granted: March 18, 2025
Patent Number:
12254933
For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV…
Combined denoising and upscaling network with importance sampling in a graphics environment
Granted: March 18, 2025
Patent Number:
12254590
An apparatus to facilitate combined denoising and upscaling network with importance sampling in a graphics environment is disclosed. The apparatus includes set of processing resources including circuitry configured to: receive, at an input of a density map neural network, a sampled signal of a current frame and a reconstructed sample of the current frame; output, from the density map neural network, a prediction of a density map of samples based on the input of the current frame; provide…
On chip dense memory for temporal buffering
Granted: March 18, 2025
Patent Number:
12254526
Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the…
Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator
Granted: March 18, 2025
Patent Number:
12254399
Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of…
Dynamic application programming interface (API) contract generation and conversion through microservice sidecars
Granted: March 18, 2025
Patent Number:
12254361
Embodiments described herein are generally directed to the use of sidecars to perform dynamic Application Programming Interface (API) contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies.…
Real-time anomaly detection for industrial processes
Granted: March 18, 2025
Patent Number:
12253849
In one embodiment, a device comprises interface circuitry and processing circuitry. The processing circuitry receives, via the interface circuitry, a video stream captured by a camera during performance of an industrial process, wherein the video stream comprises a sequence of frames; detects, based on analyzing the sequence of frames, a degree of particle scatter that occurs during performance of the industrial process; and determines, based on the degree of particle scatter, that an…
Scalable toggle point control circuitry for a clustered decode pipeline
Granted: March 18, 2025
Patent Number:
12254319
Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster,…
Firmware update techniques
Granted: March 18, 2025
Patent Number:
12254304
Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device…
Message authentication Galois integrity and correction (MAGIC) for lightweight row hammer mitigation
Granted: March 18, 2025
Patent Number:
12254203
The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.
PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states
Granted: March 18, 2025
Patent Number:
12253966
A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power…
System for address mapping and translation protection
Granted: March 18, 2025
Patent Number:
12253958
This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs)…
Methods, systems, articles of manufacture and apparatus to control address space isolation in a virtual machine
Granted: March 18, 2025
Patent Number:
12253955
Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value,…
Software-defined coherent caching of pooled memory
Granted: March 18, 2025
Patent Number:
12253948
Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete…
Technologies for configuration of memory ranges
Granted: March 18, 2025
Patent Number:
12253947
Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and…
Gating of a mesh clock signal in a processor
Granted: March 18, 2025
Patent Number:
12253877
In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated…
