Directed self-assembly enabled patterning over metal layers using assisting features
Granted: April 1, 2025
Patent Number:
12266527
Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers,…
Pillar select transistor for 3-dimensional cross point memory
Granted: April 1, 2025
Patent Number:
12268011
A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure…
Enhanced service function chaining in next generation cellular networks
Granted: April 1, 2025
Patent Number:
12267225
This disclosure describes systems, methods, and devices related to service function chaining in wireless networks. A communications system may include a communication control function to select one or multiple communication service functions associated with establishing service function chaining (SFC) services for telecommunications; a service orchestration and chaining function (SOCF) to establish the SFC services; and a service orchestration exposure function (SOEF) to expose the SFC…
Methods and devices for device orientation to improve signal quality and SAR compliance
Granted: April 1, 2025
Patent Number:
12267097
Devices and methods for automatically determining and suggesting an optimal device orientation with respect to a partner communication device. The methods and devices may include features to determine a position of a user with respect to the device; estimate a direction of a partner communication device; perform a comparison of the direction of the partner communication device with the position of the user; and based on the comparison, determine whether to generate an instruction to…
Electrical interconnect with improved impedance
Granted: April 1, 2025
Patent Number:
12266878
An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer…
Electronic substrates having heterogeneous dielectric layers
Granted: April 1, 2025
Patent Number:
12266581
An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.
Self-aligned contacts
Granted: April 1, 2025
Patent Number:
12266571
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact…
Self-aligned interconnect structures and methods of fabrication
Granted: April 1, 2025
Patent Number:
12266570
An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a…
Interconnect wires including relatively low resistivity cores
Granted: April 1, 2025
Patent Number:
12266568
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures
Granted: April 1, 2025
Patent Number:
12266536
Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a…
Collaborative multi-robot tasks using action primitives
Granted: April 1, 2025
Patent Number:
12263599
Various aspects of methods, systems, and use cases include techniques for training or using a model to control a robot. A method may include identifying a set of action primitives applicable to a set of robots, receiving information corresponding to a task (e.g., a collaborative task), and determining at least one action primitive based on the received information. The method may include training a model to control operations of at least one robot of the set of robots using the received…
NAND sensing circuit and technique for read-disturb mitigation
Granted: April 1, 2025
Patent Number:
12266406
Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through…
Cinematic space-time view synthesis for enhanced viewing experiences in computing environments
Granted: April 1, 2025
Patent Number:
12266383
A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. The method further includes…
Apparatus and method for using alpha values to improve ray tracing efficiency
Granted: April 1, 2025
Patent Number:
12266046
Apparatus and method for encoding sub-primitives to improve ray tracing efficiency. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a ray tracing graphics pipeline; a sub-primitive generator to subdivide each primitive of a plurality of primitives into a plurality of sub-primitives; a sub-primitive encoder to identify a first subset of the plurality of sub-primitives as being fully transparent and to identify a second subset of…
Apparatus and method including scalable representations of arbitrary quantum computing rotations
Granted: April 1, 2025
Patent Number:
12265885
Apparatus and method for scalable representations of arbitrary quantum computing rotations. For example, one embodiment of an apparatus comprises: a memory to store a first waveform; and a base envelope generator to implement a base envelope, the base envelope applied to the first waveform to generate a second waveform usable to cause quantum rotation of a specified angle on a target quantum bit (qubit) of a quantum processor, and wherein the base envelope is selected out of a first…
Data access ordering for writing-to or reading-from memory devices
Granted: April 1, 2025
Patent Number:
12265724
Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the…
Per channel thermal management techniques for stacked memory
Granted: April 1, 2025
Patent Number:
12265723
Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command…
Shunt-series and series-shunt inductively peaked clock buffer, and asymmetric multiplexer and de-multiplexer
Granted: April 1, 2025
Patent Number:
12265483
A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric…
Co-existence of full frame and partial frame idle image updates
Granted: April 1, 2025
Patent Number:
12265439
Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.
Device posture-based pre-boot display orientation and other usage support
Granted: April 1, 2025
Patent Number:
12265428
An example computing device comprises a processor to be coupled to a display device, and a boot controller coupled to the processor and to be coupled to the display device. The boot controller is configured to detect a power signal, receive sensor data detected by one or more sensors prior to an operating system being loaded by a boot process of the processor, determine a posture associated with the display device based on the sensor data detected by the one or more sensors, and…
