Schedule-aware tensor distribution module
Granted: April 29, 2025
Patent Number:
12288153
Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase,…
Multi-tenant isolated data regions for collaborative platform architectures
Granted: April 29, 2025
Patent Number:
12289362
A multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. Instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, MKTME), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and…
Protecting data transfer between a secure application and networked devices
Granted: April 29, 2025
Patent Number:
12289301
An apparatus to facilitate protecting data transfer between a secure application and networked devices is disclosed. The apparatus includes a processor to provide a trusted execution environment (TEE) to run an application, wherein the processor is to: generate, via the application in the TEE, encrypted data, wherein the encrypted data comprises a payload; copy, via the application in the TEE, the encrypted data to a local buffer; interface, using the application in the TEE, with a…
Dynamic load balancing for multi-core computing environments
Granted: April 29, 2025
Patent Number:
12289239
Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores…
Clock manager monitoring for time synchronized networks
Granted: April 29, 2025
Patent Number:
12289161
Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a…
Semiconductor device having tipless epitaxial source/drain regions
Granted: April 29, 2025
Patent Number:
12288821
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in…
Backside contact structures and fabrication for metal on both sides of devices
Granted: April 29, 2025
Patent Number:
12288810
An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to…
Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact
Granted: April 29, 2025
Patent Number:
12288789
Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source…
Microelectronic assemblies
Granted: April 29, 2025
Patent Number:
12288751
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
Granted: April 29, 2025
Patent Number:
12288744
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
Semiconductor package with hybrid mold layers
Granted: April 29, 2025
Patent Number:
12288740
According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a…
Graphics system with additional context
Granted: April 29, 2025
Patent Number:
12288287
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a…
Adaptively embedding visual advertising content into media content
Granted: April 29, 2025
Patent Number:
12288224
Technologies for adaptively embedding visual advertising content into media content include a computing device for receiving visual advertisements, an advertisement map, and media content from a remote content provider. Such technologies may also include determining a location of an advertising enabled area within an image of the media content, selecting a visual advertisement to embed within the image of the media content at the determined location of the advertising enabled area as a…
Assessment and response mechanism for autonomous systems
Granted: April 29, 2025
Patent Number:
12288166
Various systems and methods for implementing an assessment and response mechanism for autonomous systems are described herein. An assessment and response system for an autonomous system is configured to access a realm classification of an event; determine a hazard score based on the realm classification, a severity metric, a likelihood metric, an urgency metric, and a confidence level metric; identify, based on the hazard score, a responsive action; and record details of the hazard score…
Multi-level caching for dynamic deep learning models
Granted: April 29, 2025
Patent Number:
12288141
Systems, apparatuses and methods provide technology for model generation with intermediate stage caching and re-use, including generating, via a model pipeline, a multi-level set of intermediate stages for a model, caching each of the set of intermediate stages, and responsive to a change in the model pipeline, regenerating an executable for the model using a first one of the cached intermediate stages to bypass regeneration of at least one of the intermediate stages. The multi-level set…
Integrating artificial intelligence into vehicles
Granted: April 22, 2025
Patent Number:
12280807
Systems and methods may be used for vehicle support or operation. A method may be performed using an edge device to support operations of a vehicle. The method may include receiving a request from a vehicle component to register with an artificial intelligence processing component of the edge device, sending an acknowledgement of the registration to the vehicle component, receiving a request for a service of the artificial intelligence processing component, and providing, to the vehicle…
Converting multiple light signals into and out of a single wavelength with multiple polarizations to increase optical bandwidth
Granted: April 22, 2025
Patent Number:
12282174
Embodiments described herein may be related to apparatuses, processes, and techniques related to a dual polarization chiplet that may be used by an optical receiver to split multi-polarized light traveling on a single fiber and carrying two or more light signals into two or more fibers each carrying the particular light signal. The dual polarization chiplet may also be used by an optical transmitter to combine multiple light signals to be transmitted onto a single fiber, where each of…
System, apparatus and methods for power communications according to a CXL power protocol
Granted: April 22, 2025
Patent Number:
12282366
In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least…
Hardware-assisted core frequency and voltage scaling in a poll mode idle loop
Granted: April 22, 2025
Patent Number:
12282377
A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core…
Techniques for memory access in a reduced power state
Granted: April 22, 2025
Patent Number:
12282378
Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may…
