Cinematic space-time view synthesis for enhanced viewing experiences in computing environments
Granted: April 1, 2025
Patent Number:
12266383
A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. The method further includes…
Pillar select transistor for 3-dimensional cross point memory
Granted: April 1, 2025
Patent Number:
12268011
A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure…
Enhanced service function chaining in next generation cellular networks
Granted: April 1, 2025
Patent Number:
12267225
This disclosure describes systems, methods, and devices related to service function chaining in wireless networks. A communications system may include a communication control function to select one or multiple communication service functions associated with establishing service function chaining (SFC) services for telecommunications; a service orchestration and chaining function (SOCF) to establish the SFC services; and a service orchestration exposure function (SOEF) to expose the SFC…
Transistors with monocrystalline metal chalcogenide channel materials
Granted: April 1, 2025
Patent Number:
12266720
Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal…
Transition metal dichalcogenide nanosheet transistors and methods of fabrication
Granted: April 1, 2025
Patent Number:
12266712
A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel…
Integrated circuit structures having dielectric anchor void
Granted: April 1, 2025
Patent Number:
12266708
Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric…
Quantum dot array devices with shared gates
Granted: April 1, 2025
Patent Number:
12266699
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
Integrated photonics and processor package with redistribution layer and EMIB connector
Granted: April 1, 2025
Patent Number:
12266608
Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or…
Electronic substrates having heterogeneous dielectric layers
Granted: April 1, 2025
Patent Number:
12266581
An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.
NAND sensing circuit and technique for read-disturb mitigation
Granted: April 1, 2025
Patent Number:
12266406
Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through…
Systems for performing instructions to quickly convert and use tiles as 1D vectors
Granted: April 1, 2025
Patent Number:
12265826
Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the…
Data access ordering for writing-to or reading-from memory devices
Granted: April 1, 2025
Patent Number:
12265724
Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the…
Device posture-based pre-boot display orientation and other usage support
Granted: April 1, 2025
Patent Number:
12265428
An example computing device comprises a processor to be coupled to a display device, and a boot controller coupled to the processor and to be coupled to the display device. The boot controller is configured to detect a power signal, receive sensor data detected by one or more sensors prior to an operating system being loaded by a boot process of the processor, determine a posture associated with the display device based on the sensor data detected by the one or more sensors, and…
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
Granted: March 25, 2025
Patent Number:
12261122
Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench…
Channel access related enhancements to new radio unlicensed (NR-U)
Granted: March 25, 2025
Patent Number:
12261727
Various embodiments herein provide techniques for wireless communication on New Radio unlicensed (NR-U) spectrum. For example, embodiments include techniques for a new listen-before-talk type and associated measurement window. Additionally, embodiments include techniques for determination of a cyclic prefix (CP) extension for an uplink transmission, such as a configured grant transmission or a dynamically scheduled transmission. Other embodiments may be described and claimed.
SERDES circuit automatic gain control and convergence
Granted: March 25, 2025
Patent Number:
12261724
An Automatic Gain Control (AGC) SERDES circuit may be used to provide improved gain control for SERDES operation. This AGC SERDES circuit uses an initial gain convergence to determine and store an initial gain level. Once the initial gain convergence is complete, the AGC SERDES circuit uses a signal peak tracking to reduce or prevent saturation events. By setting the gain target based on tracked changes in the equalizer coefficients, the AGC SERDES circuit adapts the gain target to…
Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver
Granted: March 25, 2025
Patent Number:
12261637
A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is…
Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter
Granted: March 25, 2025
Patent Number:
12261622
Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third…
Computational current sensor
Granted: March 25, 2025
Patent Number:
12261526
A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current…
Apparatus, and system of a stack series fed antenna including a plurality of antenna layers
Granted: March 25, 2025
Patent Number:
12261378
For example, an apparatus may include a radome; and a stack series fed antenna including a plurality of antenna layers, the plurality of antenna layers including a first antenna layer on an inner surface of the radome, the first antenna layer including a first plurality of serially connected antenna elements, and a first trace configured to drive an electrical current from a power source to the first plurality of serially connected antenna elements; and a second antenna layer covered by…
