Apparatus, system and method of communicating a multi-link element
Granted: May 7, 2024
Patent Number:
11979925
For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of…
Automatic profiling of application workloads in a performance monitoring unit using hardware telemetry
Granted: May 7, 2024
Patent Number:
11977468
A performance monitoring unit of a processor includes one or more performance monitoring counters, and a behavioral detector to sample data from a set of the one or more performance monitoring counters, analyze the sampled data, and identify a type of workload of a software process being executed by the processor.
Normalized probability determination for character encoding
Granted: April 30, 2024
Patent Number:
11973519
Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for…
Online compensation of thermal distortions in a stereo depth camera
Granted: April 30, 2024
Patent Number:
11973923
An example apparatus includes: a camera to record an image; memory to store instructions; and a processor in circuit with the memory, the processor to execute the instructions to: determine a depth based on: (a) the image and (b) a calibration parameter of the camera; and adjust the calibration parameter based on a temperature of the camera and the depth.
User-configurable data prioritization
Granted: April 30, 2024
Patent Number:
11973689
A processor may control a transmitter to send a first signal representing a request for one or more priority rules for data packet prioritization; to receive a second signal in response to the first signal, the second signal representing the one or more priority rules for data packet prioritization, and to receive a third signal representing a data packet including a header and a data payload. The header may comprise a first priority tag representing a first priority level. The processor…
Enhanced frame exchange and multi-link device messaging for secure communications
Granted: April 30, 2024
Patent Number:
11973679
This disclosure describes systems, methods, and devices related to enhanced frame exchange. A device may generate a first subset of a plurality of fields, wherein the first subset is mandatory in a probe request frame. The device may generate a second subset of the plurality of fields, wherein the second subset is optional in the probe request frame regardless of capability information of the device. The device may generate the probe request frame comprising the first subset and the…
Deploying edge computing
Granted: April 30, 2024
Patent Number:
11973641
Techniques discussed herein can facilitate edge computing in connection with a variety of deployment scenarios. Various embodiments can facilitate one or more of: deploying UPF(s) (User Plane Function(s)) to support edge computing; removing UPF(s) not needed for edge computing; deploying local DN(s) (Data Network(s)); E2E (Edge-to-Edge) OSS (Operations Support System) deployment scenarios; and providing RAN (Radio Access Network) condition data to support various applications (e.g.,…
Extended link-training time negotiated on link start-up
Granted: April 30, 2024
Patent Number:
11973624
Examples described herein relate to link training between network connected devices. In some examples, an amount to extend link training is determined. The amount to extend link training can be determined by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals indicating capability to extend link training time and amount to extend link training time; determining, at the first device, a link training time based on a default…
Algorithm and architecture for channel estimation in 5G new radio
Granted: April 30, 2024
Patent Number:
11973618
This disclosure relates to apparatuses, systems, and methods for channel estimation, and in particular channel estimation for 5G New Radio systems. The channel estimation interpolates, prior to performing a de-spreading operation, a first combined channel estimation and a second combined channel estimation to provide from the first combined channel estimation one or more channel estimation values at indices associated with the second combined channel estimation and/or to provide from the…
Optical transceivers with multi-laser modules
Granted: April 30, 2024
Patent Number:
11973539
Disclosed herein are optical transceivers with multi-laser modules, as well as related optoelectronic assemblies and methods. In some embodiments, an optical transceiver may include: a first laser and a second laser; an optical output path, wherein an output of the first laser is coupled to the optical output path; and switching circuitry to decouple the output of the first laser from the optical output path and to couple an output of the second laser to the optical output path.
Quality of service rules in allocating processor resources
Granted: April 30, 2024
Patent Number:
11972291
An apparatus and method for conditional quality of service in a processor. For example, one embodiment of a processor comprises: a plurality of processor resources to be allocated to a plurality of executed processes in accordance with a set of quality of service (QoS) rules; and conditional quality of service (QoS) circuitry/logic to monitor usage of the plurality of processor resources by the plurality of processes and to responsively modify an allocation of a first processor resource…
Multi-reset and multi-clock synchronizer, and synchronous multi-cycle reset synchronization circuit
Granted: April 30, 2024
Patent Number:
11973504
An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that…
Source or drain structures for germanium N-channel devices
Granted: April 30, 2024
Patent Number:
11973143
Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an…
Device contacts in integrated circuit structures
Granted: April 30, 2024
Patent Number:
11973121
Discussed herein are device contacts in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact; a gate contact, wherein the gate contact is in contact with a gate and with the first S/D contact; and a second S/D contact, wherein a height of the second S/D contact is less than a height of the first S/D contact.
Embedded precision resistor for non-planar semiconductor device architectures
Granted: April 30, 2024
Patent Number:
11973105
An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and…
Chiplet first architecture for die tiling applications
Granted: April 30, 2024
Patent Number:
11973041
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further…
Internal node jumper for memory bit cells
Granted: April 30, 2024
Patent Number:
11973032
Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate…
Apparatus and method of guided neural network model for image processing
Granted: April 30, 2024
Patent Number:
11972545
The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize…
Learning neural reflectance shaders from images
Granted: April 30, 2024
Patent Number:
11972519
Described herein are techniques for learning neural reflectance shaders from images. A set of one or more machine learning models can be trained to optimize an illumination latent code and a set of reflectance latent codes for an object within a set of input images. A shader can then be generated based on a machine learning model of the one or more machine learning models. The shader is configured to sample the illumination latent code and the set of reflectance latent codes for the…
Technologies for data migration between edge accelerators hosted on different edge locations
Granted: April 30, 2024
Patent Number:
11972298
Technologies for migrating data between edge accelerators hosted on different edge locations include a device hosted on a present edge location. The device includes one or more processors to: receive a workload from a requesting device, determine one or more accelerator devices hosted on the present edge location to perform the workload, and transmit the workload to the one or more accelerator devices to process the workload. The one or more processor is further to determine whether to…
