Latency offset in pre-clock tree synthesis modeling
Granted: June 20, 2023
Patent Number:
11681842
Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint…
Interconnect repeater planning and implementation flow for abutting designs
Granted: June 13, 2023
Patent Number:
11675726
A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes,…
Sequential delay enabler timer circuit for low voltage operation for SRAMs
Granted: June 6, 2023
Patent Number:
11670361
An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains…
Automatic test pattern generation (ATPG) for parametric faults
Granted: June 6, 2023
Patent Number:
11669667
Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
Granted: June 6, 2023
Patent Number:
11669665
A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.
Tuning analog front end response for jitter tolerance margins
Granted: May 30, 2023
Patent Number:
11665031
A method for tuning an analog front end response is provided. The method includes determining a peaking control value for an analog front end (AFE) of a receiver, determining an attribute corresponding to the peaking control value, selecting the peaking control value as the operating peaking control value for the AFE based on the attribute being determined to be higher than a previous attribute, and performing a receiver adaptation using the peaking control for a one or more transmitter…
Classification of patterns in an electronic circuit layout using machine learning based encoding
Granted: May 30, 2023
Patent Number:
11663485
A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The…
Timing modeling of multi-stage cells using both behavioral and structural models
Granted: May 30, 2023
Patent Number:
11663384
An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then…
High-speed functional protocol based test and debug
Granted: May 30, 2023
Patent Number:
11662383
An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control…
Multi-port—multi mode Reed Solomon decoder
Granted: May 23, 2023
Patent Number:
11658684
A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together…
Wafer sensitivity determination and communication
Granted: May 23, 2023
Patent Number:
11657207
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.
Construction, modeling, and mapping of multi-output cells
Granted: May 23, 2023
Patent Number:
11657205
A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second…
Independent skew control of a multi-phase clock
Granted: May 16, 2023
Patent Number:
11652475
A circuit includes, in part, a first transistor receiving a first clock signal at its gate, a second transistor receiving a second clock signal at its gate, a first impedance coupled to the drain terminal of the first transistor, a second impedance coupled to the drain terminal of the second transistor, a current source coupled to the source terminals of the first and second transistors, a third transistor receiving a third clock signal at its gate, a fourth transistor receiving a fourth…
Low latency decoder for error correcting codes
Granted: May 16, 2023
Patent Number:
11651830
A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The…
Dose optimization techniques for mask synthesis tools
Granted: May 16, 2023
Patent Number:
11651135
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.
Glitch source identification and ranking
Granted: May 16, 2023
Patent Number:
11651131
Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch…
Selecting a subset of training data from a data pool for a power prediction model
Granted: May 16, 2023
Patent Number:
11651129
A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting…
Inverse etch model for mask synthesis
Granted: May 9, 2023
Patent Number:
11644746
A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between…
Inverse etch model for mask synthesis
Granted: May 9, 2023
Patent Number:
11644746
A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between…
Obtaining a mask using a cost function gradient from a jacobian matrix generated from a perturbation look-up table
Granted: May 9, 2023
Patent Number:
11644747
Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask…
