Fin patterning to reduce fin collapse and transistor leakage
Granted: October 3, 2023
Patent Number:
11776816
At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.
High speed, low hardware footprint waveform
Granted: October 3, 2023
Patent Number:
11775716
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces…
System and method for auditing a graph-based API
Granted: October 3, 2023
Patent Number:
11775363
A method for auditing a graph-based API includes obtaining a structure describing object types of the API and fields of the object types. A schema graph of the structure is generated including nodes representing object types. The nodes are connected by directed edges representing field resolution between object types. A line graph is generated and includes a node in place of each edge of the schema graph and edges in place of nodes of the schema graph. Frontiers of the line graph are…
Aging-resistant Schmitt receiver circuit
Granted: September 19, 2023
Patent Number:
11764765
A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
Net-based wafer inspection
Granted: September 19, 2023
Patent Number:
11763059
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are…
Method and system for custom model definition of analog defects in an integrated circuit
Granted: September 19, 2023
Patent Number:
11763056
A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied,…
Coherent observability and controllability of overlaid clock and data propagation in emulation and prototyping
Granted: September 19, 2023
Patent Number:
11763053
The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed.…
Inverse lithography and machine learning for mask synthesis
Granted: September 19, 2023
Patent Number:
11762283
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108).…
Latency offset in pre-clock tree synthesis modeling
Granted: June 20, 2023
Patent Number:
11681842
Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint…
On-the-fly multi-bit flip flop generation
Granted: June 20, 2023
Patent Number:
11681848
On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.
Interconnect repeater planning and implementation flow for abutting designs
Granted: June 13, 2023
Patent Number:
11675726
A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes,…
Sequential delay enabler timer circuit for low voltage operation for SRAMs
Granted: June 6, 2023
Patent Number:
11670361
An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains…
Automatic test pattern generation (ATPG) for parametric faults
Granted: June 6, 2023
Patent Number:
11669667
Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
Granted: June 6, 2023
Patent Number:
11669665
A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.
Tuning analog front end response for jitter tolerance margins
Granted: May 30, 2023
Patent Number:
11665031
A method for tuning an analog front end response is provided. The method includes determining a peaking control value for an analog front end (AFE) of a receiver, determining an attribute corresponding to the peaking control value, selecting the peaking control value as the operating peaking control value for the AFE based on the attribute being determined to be higher than a previous attribute, and performing a receiver adaptation using the peaking control for a one or more transmitter…
Classification of patterns in an electronic circuit layout using machine learning based encoding
Granted: May 30, 2023
Patent Number:
11663485
A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The…
Timing modeling of multi-stage cells using both behavioral and structural models
Granted: May 30, 2023
Patent Number:
11663384
An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then…
High-speed functional protocol based test and debug
Granted: May 30, 2023
Patent Number:
11662383
An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control…
Construction, modeling, and mapping of multi-output cells
Granted: May 23, 2023
Patent Number:
11657205
A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second…
Wafer sensitivity determination and communication
Granted: May 23, 2023
Patent Number:
11657207
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.
