FPGA-based hardware emulator system with an inter-FPGA connection switch
Granted: December 7, 2021
Patent Number:
11194943
A hardware emulation system for emulating an integrated circuit design under test (DUT) includes a switch system, FPGAs and serial transmitter and receiver circuitry. The switch system has input and output ports and is configurable to change which ports are connected to each other. The FPGAs are configurable to emulate a functionality of the DUT. The functionality of the DUT is partitioned across multiple FPGAs. The serial transmitter circuitry transmits data from the FPGAs on serial…
Pin accessibility prediction engine
Granted: November 30, 2021
Patent Number:
11188705
An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin…
Placement and routing of cells using cell-level layout-dependent stress effects
Granted: November 30, 2021
Patent Number:
11188699
Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a…
Unified functional coverage and synthesis flow for formal verification and emulation
Granted: November 30, 2021
Patent Number:
11188695
Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part…
High-performance learning-ready platform for real-time analytics
Granted: November 30, 2021
Patent Number:
11188508
A system and method for operating a high-performance learning-ready platform for real-time analytics involves operating a collector to collect logging data from electronic design automation (EDA) tools. The collector operates either (A) a set of programming interface (i.e., function calls) integrated with an EDA tool, or (B) a selector to extract the logging data from EDA tool logs. The collector generates data logs in a key-value pair data logging format from the logging data. A memory…
Reflective EUV mask absorber manipulation to improve wafer contrast
Granted: November 30, 2021
Patent Number:
11187973
Techniques and systems for improving wafer contrast by manipulating reflective extreme ultraviolet (EUV) mask absorber are described. Some embodiment disclosed herein provide for EUV absorber material, which transmits some EUV illumination, to suppress the printing of sub-resolution assist features (SRAFs) while making the SRAFs closer in size to the printed feature by thinning the SRAF absorber thickness from the nominal mask absorber thickness in the bright-field mask case. In the…
Power harvesting for integrated circuits
Granted: November 16, 2021
Patent Number:
11177317
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…
Methods and systems to perform automated Integrated Fan-Out wafer level package routing
Granted: November 16, 2021
Patent Number:
11176306
A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph.…
Method and system for emulation clock tree reduction
Granted: November 16, 2021
Patent Number:
11176293
The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone…
Tools for coupling and decoupling a cable connector
Granted: November 9, 2021
Patent Number:
11171460
A tool for coupling and decoupling a connector of a cable. The tool includes a body, a bracket, and a first hook. The body has a first end portion, a second end portion opposite the first end portion, and an intermediate portion between the first end portion and the second end portion. The body has a longitudinal axis running between the first end portion and second end portion. The body also has a first surface and a second surface opposite the first surface. The bracket is disposed at…
SRAM and periphery specialized device sensors
Granted: November 2, 2021
Patent Number:
11164624
A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.
Single phase clock-gating circuit
Granted: October 26, 2021
Patent Number:
11159163
A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second…
Using threading dislocations in GaN/Si systems to generate physically unclonable functions
Granted: October 19, 2021
Patent Number:
11152313
The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction…
Emulated register access in hybrid emulation
Granted: October 19, 2021
Patent Number:
11151294
One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation…
One time programmable anti-fuse physical unclonable function
Granted: October 12, 2021
Patent Number:
11145344
A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first…
Smart repeater design for on-route repeater planning for bus
Granted: October 12, 2021
Patent Number:
11144703
A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib…
Grouping nets to facilitate repeater insertion
Granted: October 12, 2021
Patent Number:
11144700
Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.
Extensible layer mapping for in-design verification
Granted: October 12, 2021
Patent Number:
11144690
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of…
Dedicated reconfigurable IP for emulation-based power estimation
Granted: October 5, 2021
Patent Number:
11138356
A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.
Crystal orientation engineering to achieve consistent nanowire shapes
Granted: October 5, 2021
Patent Number:
11139402
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a…
