Mask rule checking for curvilinear masks for electronic circuits
Granted: January 11, 2022
Patent Number:
11222160
A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two…
Method and apparatus for reducing pessimism of graph based static timing analysis
Granted: January 11, 2022
Patent Number:
11222155
Disclosed is a method and apparatus that takes timing information associated with a plurality of inputs to a cell, such as an AND-gate, within an integrated circuit (IC) design, store the timing information in a timing information register (TIR) associated with an index identifying the source of the timing information and track the source of the timing information for a predetermined number of cells through the index. The timing information in the TIRs is merged upon the index indicating…
State table complexity reduction in a hierarchical verification flow
Granted: January 11, 2022
Patent Number:
11222154
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical…
Combinatorial and sequential logic compaction in electronic circuit design emulation
Granted: January 11, 2022
Patent Number:
11221864
An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation…
Mitigating timing yield loss due to high-sigma rare-event process variation
Granted: December 28, 2021
Patent Number:
11210448
Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is…
3D resist profile aware resolution enhancement techniques
Granted: December 14, 2021
Patent Number:
11200362
Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.
Waveform based reconstruction for emulation
Granted: December 14, 2021
Patent Number:
11200149
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
Automated self-check of a closed loop emulation replay
Granted: December 14, 2021
Patent Number:
11200127
A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting…
FPGA-based hardware emulator system with an inter-FPGA connection switch
Granted: December 7, 2021
Patent Number:
11194943
A hardware emulation system for emulating an integrated circuit design under test (DUT) includes a switch system, FPGAs and serial transmitter and receiver circuitry. The switch system has input and output ports and is configurable to change which ports are connected to each other. The FPGAs are configurable to emulate a functionality of the DUT. The functionality of the DUT is partitioned across multiple FPGAs. The serial transmitter circuitry transmits data from the FPGAs on serial…
Predictor-guided cell spreader to improve routability for designs at advanced process nodes
Granted: December 7, 2021
Patent Number:
11194949
A routability optimization engine comprising a hotspot prediction engine to predict locations of a plurality of hotspots in a circuit layout based on a machine learning system, a white space calculator to calculate white space around each of the plurality of hotspots, and a cell spreader engine to redistribute white space around each of the plurality of hotspots to improve routability of the circuit layout.
Pin accessibility prediction engine
Granted: November 30, 2021
Patent Number:
11188705
An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin…
Placement and routing of cells using cell-level layout-dependent stress effects
Granted: November 30, 2021
Patent Number:
11188699
Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a…
Unified functional coverage and synthesis flow for formal verification and emulation
Granted: November 30, 2021
Patent Number:
11188695
Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part…
High-performance learning-ready platform for real-time analytics
Granted: November 30, 2021
Patent Number:
11188508
A system and method for operating a high-performance learning-ready platform for real-time analytics involves operating a collector to collect logging data from electronic design automation (EDA) tools. The collector operates either (A) a set of programming interface (i.e., function calls) integrated with an EDA tool, or (B) a selector to extract the logging data from EDA tool logs. The collector generates data logs in a key-value pair data logging format from the logging data. A memory…
Reflective EUV mask absorber manipulation to improve wafer contrast
Granted: November 30, 2021
Patent Number:
11187973
Techniques and systems for improving wafer contrast by manipulating reflective extreme ultraviolet (EUV) mask absorber are described. Some embodiment disclosed herein provide for EUV absorber material, which transmits some EUV illumination, to suppress the printing of sub-resolution assist features (SRAFs) while making the SRAFs closer in size to the printed feature by thinning the SRAF absorber thickness from the nominal mask absorber thickness in the bright-field mask case. In the…
Power harvesting for integrated circuits
Granted: November 16, 2021
Patent Number:
11177317
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…
Methods and systems to perform automated Integrated Fan-Out wafer level package routing
Granted: November 16, 2021
Patent Number:
11176306
A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph.…
Method and system for emulation clock tree reduction
Granted: November 16, 2021
Patent Number:
11176293
The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone…
Tools for coupling and decoupling a cable connector
Granted: November 9, 2021
Patent Number:
11171460
A tool for coupling and decoupling a connector of a cable. The tool includes a body, a bracket, and a first hook. The body has a first end portion, a second end portion opposite the first end portion, and an intermediate portion between the first end portion and the second end portion. The body has a longitudinal axis running between the first end portion and second end portion. The body also has a first surface and a second surface opposite the first surface. The bracket is disposed at…
SRAM and periphery specialized device sensors
Granted: November 2, 2021
Patent Number:
11164624
A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.
