Single phase clock-gating circuit
Granted: October 26, 2021
Patent Number:
11159163
A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second…
Using threading dislocations in GaN/Si systems to generate physically unclonable functions
Granted: October 19, 2021
Patent Number:
11152313
The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction…
Emulated register access in hybrid emulation
Granted: October 19, 2021
Patent Number:
11151294
One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation…
One time programmable anti-fuse physical unclonable function
Granted: October 12, 2021
Patent Number:
11145344
A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first…
Smart repeater design for on-route repeater planning for bus
Granted: October 12, 2021
Patent Number:
11144703
A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib…
Grouping nets to facilitate repeater insertion
Granted: October 12, 2021
Patent Number:
11144700
Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.
Extensible layer mapping for in-design verification
Granted: October 12, 2021
Patent Number:
11144690
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of…
Crystal orientation engineering to achieve consistent nanowire shapes
Granted: October 5, 2021
Patent Number:
11139402
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a…
Dedicated reconfigurable IP for emulation-based power estimation
Granted: October 5, 2021
Patent Number:
11138356
A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.
Magnetoresistive random access memory (MRAM) bit cell with a narrow write window distribution
Granted: September 28, 2021
Patent Number:
11133045
A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.
DRC processing tool for early stage IC layout designs
Granted: September 28, 2021
Patent Number:
11132491
A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined…
Controlling clocks and resets in a logic built in self-test
Granted: September 28, 2021
Patent Number:
11132484
A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.
Applying reticle enhancement technique recipes based on failure modes predicted by an artificial neural network
Granted: September 21, 2021
Patent Number:
11126782
Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural…
Automatic net grouping and routing
Granted: September 21, 2021
Patent Number:
11126780
Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing…
Satisfiability sweeping for synthesis
Granted: September 14, 2021
Patent Number:
11120184
A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the…
Memory migration in hybrid emulation
Granted: September 7, 2021
Patent Number:
11113440
A hybrid emulation system and method for hybrid emulation of a design under test (DUT). The DUT has system memory logically segmented into a plurality of memory blocks. The hybrid emulation system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. At least one of the hardware emulation system or the…
Determining security vulnerabilities in application programming interfaces
Granted: August 31, 2021
Patent Number:
11108803
A security system scans application programming interfaces (APIs) to detect security vulnerabilities by receiving API documentation from a third-party system associated with the API and organizing it in an API specification that describes the hostname of the API and one or more endpoints of the API. For each of the endpoints, the API specification includes a uniform resource identifier, a method term, an input content type, an output content type (if applicable), authorization details,…
Speeding matching search of hierarchical name structures
Granted: August 31, 2021
Patent Number:
11106663
A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression,…
Pattern based die connector assignment using machine learning image recognition
Granted: August 24, 2021
Patent Number:
11100270
A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical…
Seamless transition between routing modes
Granted: August 24, 2021
Patent Number:
11100271
Seamless transitions between routing modes are provided via providing a cursor in association with a design layout; in response to receiving a follow-the-cursor (FTC) command at a first position in the design layout, create a first trace in the design layout where the cursor is displayed; in response to receiving a start command for point-to-point routing at a second position in the design layout: complete the first trace at the second position; and provide an indicator at the second…
