Pattern based die connector assignment using machine learning image recognition
Granted: August 24, 2021
Patent Number:
11100270
A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical…
Design-prioritized mask correction
Granted: August 17, 2021
Patent Number:
11093680
The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during…
Three-dimensional NoC reliability evaluation
Granted: August 17, 2021
Patent Number:
11093673
Methods, storage mediums, and apparatuses for evaluating the reliability of Three-Dimensional (3D) Network-on-Chip (NoC) designs are described. The described embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments automate the whole process of static and dynamic fault injection base on the user preference and reports the specific reliability metrics for 3D NoC…
Phase-shifting encoding for signal transition minimization
Granted: August 10, 2021
Patent Number:
11088705
A method of encoding a stream of data bits includes encoding a bit 1 of the data stream as a first symbol if a bit immediately preceding the bit 1 is encoded as 0 and a bit of the data stream immediately succeeding the bit 1 is 0, encoding the bit immediately succeeding the bit 1 as 1, encoding a bit 0 of the data stream as a second symbol if a bit immediately preceding the bit 0 is encoded as 1 and a bit of the data stream immediately succeeding the bit 0 is 1, and encoding the bit…
Clock domain crossing verification of integrated circuit design using parameter inference
Granted: August 10, 2021
Patent Number:
11087059
Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (102). The design includes a first parameterized element and a second parameterized element (104). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (106). A plurality of models relating to the design are generated by a processing device (110). A first value of the first…
Calculating inductance based on a netlist
Granted: August 3, 2021
Patent Number:
11080450
A netlist may include a set of resistance components of an integrated circuit (IC) design, and may specify a length, a width, and a metal layer of each resistance component in the set of resistance components, and physical locations of circuit nodes connected to each resistance component in the set of resistance components. A process description may specify the resistivity and thickness of each metal layer in the IC design. For a resistance component in the set of resistance components,…
Method to regulate clock frequencies of hybrid electronic systems
Granted: August 3, 2021
Patent Number:
11080446
A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is…
Semiconductor digital logic circuitry for non-quantum enablement of quantum algorithms
Granted: August 3, 2021
Patent Number:
11079790
Circuitry and processes are disclosed that use conventional electronic circuits (comprising, for example, phase locked loops, pulse width modulators, phase modulators, digital logic gates, etc.) to enable quantum algorithms. Such circuitry and processes achieve the requirement for non-quantum devices to enable quantum algorithms: the tensor product entanglement of signals representing quantum states. Such circuitry and processes are readily usable by current Electronic Design Automation…
First principles design automation tool
Granted: July 20, 2021
Patent Number:
11068631
An electronic design automation tool includes an application program interface API which includes a set of parameters and procedures supporting atomistic scale modeling of electronic materials. The procedures include a procedure to execute first principles calculations, a procedure to process results from the first principles calculations to extract device scale parameters from the results, a procedure to determine whether the extracted device scale parameters lie within a specified…
Enhanced read sensing margin and minimized VDD for SRAM cell arrays
Granted: July 13, 2021
Patent Number:
11062766
A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS…
Post-ECC CRC for DDR CRC retry performance improvement
Granted: July 13, 2021
Patent Number:
11061767
A system and a method are disclosed for error correction during operations of a memory system. For example, during a read operation, the error correction includes a read retry determination to account for link errors that are detectable by cyclic redundancy check (CRC) but not correctable by error correction coding (ECC). Reducing the number of read retry operations performed may improve system performance by reducing the number of clock cycles spent on retry operations that could have…
Obtaining a mask using a cost function gradient from a Jacobian matrix generated from a perturbation look-up table
Granted: July 13, 2021
Patent Number:
11061321
Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask…
Method for detecting libraries in program binaries
Granted: June 29, 2021
Patent Number:
11048798
This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to…
Deep learning for fixability prediction of power/ground via DRC violations
Granted: June 22, 2021
Patent Number:
11042806
A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include receiving a first circuit design pattern including a DRC violation and generating a first pattern matrix based on the first circuit design pattern, and updating the first circuit design pattern, based on the first pattern matrix, to fix the DRC violation. The operations may also include determining a possibility…
Automatic testbench generator for test-pattern validation
Granted: June 15, 2021
Patent Number:
11036907
Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of…
Capturing routing intent by using a multi-level route pattern description language
Granted: June 8, 2021
Patent Number:
11030375
Techniques and systems for capturing and using routing intent in an integrated circuit (IC) design are described. Some embodiments use a graphical user interface (GUI) to capture routing intent for a net, wherein the routing intent includes a set of circuit objects associated with the net, a routing pattern, and optionally a set of user-provided attribute values. Next, the embodiments provide the routing intent to a router, wherein the router uses the routing intent to route the net.
Interactive verification of security vulnerability detections using runtime application traffic
Granted: June 8, 2021
Patent Number:
11030318
An application service request is parsed to identify an application service request parameter of the application service request. The application service request parameter is altered. The application service request is reconstructed to include the altered application service request parameter. The behavior of the application is analyzed while executing the reconstructed application service request to detect a security vulnerability. The detection of the security vulnerability is verified…
Rail block context generation for block-level rail voltage drop analysis
Granted: June 1, 2021
Patent Number:
11022634
A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop…
Detection of address errors in memory devices using multi-segment error detection codes
Granted: June 1, 2021
Patent Number:
11023310
A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one…
Method of modeling e-beam photomask manufacturing process using image-based artificial neural networks
Granted: June 1, 2021
Patent Number:
11022966
An image-based Artificial Neural Networks (ANN) is used for photomask modeling, which can self-construct an internal representation of the photomask manufacturing process, therefore allowing the modeling process to become unfettered by the limitations of existing mathematical/statistical tools, thus greatly reduces/eliminates the effort needed from tedious and costly model-builders. The ANN model requires mask layout data converted into image pixel form. In ANN training phase a first…
