Method of modeling e-beam photomask manufacturing process using image-based artificial neural networks
Granted: June 1, 2021
Patent Number:
11022966
An image-based Artificial Neural Networks (ANN) is used for photomask modeling, which can self-construct an internal representation of the photomask manufacturing process, therefore allowing the modeling process to become unfettered by the limitations of existing mathematical/statistical tools, thus greatly reduces/eliminates the effort needed from tedious and costly model-builders. The ANN model requires mask layout data converted into image pixel form. In ANN training phase a first…
Rail block context generation for block-level rail voltage drop analysis
Granted: June 1, 2021
Patent Number:
11022634
A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop…
Hybrid evolutionary algorithm for triple-patterning
Granted: May 25, 2021
Patent Number:
11018016
A method is presented for layout decomposition including creating a first graph representative of an integrated circuit layout to be multiple-patterned, when a computer is invoked to decompose the layout, and decomposing each of a first subset of a multitude of sub-graphs into at least three sets when a valid coloring solution is returned for the layout. The multitude of sub-graphs is created from the first graph by dividing the first graph. The method further includes approximately…
Memory bypass function for a memory
Granted: May 25, 2021
Patent Number:
11017873
A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit…
Knowledge-based analog layout generator
Granted: May 18, 2021
Patent Number:
11010528
A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
Efficient mechanism for interactive fault analysis in formal verification environment
Granted: May 18, 2021
Patent Number:
11010522
In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This…
Scalable boolean methods in a modern synthesis flow
Granted: May 18, 2021
Patent Number:
11010511
Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments…
Method to enable multiple users of embedded-software debug to share a single hardware resource
Granted: May 11, 2021
Patent Number:
11003819
The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for…
Recording and recreating interface navigation processes based on a whitelist generated by a machine-learned model
Granted: May 4, 2021
Patent Number:
10996966
A computer system records and recreates an interface navigation process performed by a user with a host system. The computer system observes the user's interactions with the various UI elements during an interface navigation process by using a browser extension for the browser application in which the user is performing the interface navigation process. The browser extension then stores information about the interactions the user is performing and the UI elements that they are being…
Creating gateway model routing sub-templates
Granted: April 27, 2021
Patent Number:
10990743
A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding…
System and method for generating a cluster-based power architecture user interface
Granted: April 27, 2021
Patent Number:
10990735
A system and method generates cluster-based power architecture interfaces for an integrated circuit (IC) design under test (DUT) debugging by receiving design data for an IC DUT, determining power characteristic data for the IC DUT, generating display components within a graphical user interface (GUI) corresponding to individual components encompassed within a power intent hierarchy corresponding with the IC DUT, generating graphical links between displayed components, overlaying…
FinFET cell architecture with insulator structure
Granted: April 27, 2021
Patent Number:
10990722
A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the…
Electronic virtual layer
Granted: April 27, 2021
Patent Number:
10990077
A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further…
Fractional divider
Granted: April 20, 2021
Patent Number:
10985761
A fractional divider is described herein which effectively performs an integer division followed by phase shifting, pulse swallowing, and/or multiplexing to realize a fractional divisor. The fractional divider divides an input clocking signal by a first integer divisor in a first mode of operation or by a second integer divisor in a second mode of operation to provide a first phase of a divided digital signal. Thereafter, the fractional divider shifts the first phase of the divided…
Memory array architectures for memory queues
Granted: April 20, 2021
Patent Number:
10983725
Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In…
Method and apparatus for USB periodic scheduling optimization
Granted: April 6, 2021
Patent Number:
10970004
A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may…
Clock generation and correction circuit
Granted: April 6, 2021
Patent Number:
10972105
A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern.…
Method and apparatus for memory noise-free wake-up protocol from power-down
Granted: April 6, 2021
Patent Number:
10971218
A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate…
Identifying root cause of layout versus schematic errors
Granted: April 6, 2021
Patent Number:
10970456
A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values…
Generation of module and system-level waveform signatures to verify, regression test and debug SoC functionality
Granted: April 6, 2021
Patent Number:
10970443
A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference…
