Common mode logic based quadrature coupled injection locked frequency divider with internal power-supply jitter compensation
Granted: August 6, 2024
Patent Number:
12057839
A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of…
Automatic tracking for clock synchronization based on delay line adjustment
Granted: July 30, 2024
Patent Number:
12051481
A method includes: receiving a data signal (DQ) and a clock signal (DQS); generating an indicator signal by: delaying the data signal (DQ) to generate a delayed data signal (DQ?); sampling the data signal (DQ) and the delayed data signal (DQ?) using an edge of the clock signal (DQS) to generate a first sampled value and a second sampled value; and generating the indicator signal based on the first sampled value and the second sampled value; and adjusting one or more of a DQ adjustable…
Conversion of a clean unique request to a read unique request by a memory coherency manager circuit
Granted: July 23, 2024
Patent Number:
12045167
A system and method mitigates conflicts between clean unique requests by receiving a first clean unique request from a first processor core and a second clean unique request from a second processor core. The first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory. The memory is coupled to the first processor core and the second processor core. The first clean…
Test case selection and ordering with covert minimum set cover for functional qualification
Granted: July 23, 2024
Patent Number:
12045158
Techniques and systems for test case selection and ordering with covert minimum set cover for functional qualification are described. Some embodiments can determine a first set of test cases by, iteratively, identifying a set of faults that is covered by a smallest set of test cases, determining whether or not a test case that covers a fault is able to detect the fault, and selecting and adding a test case to the first set of test cases. Next, the embodiments can execute a minimum set…
Machine learning technique to diagnose software crashes
Granted: July 23, 2024
Patent Number:
12045124
A method includes receiving a crash signature and a crash configuration. The crash signature is generated in response to a software crash in a software application caused by the crash configuration. The method also includes applying a first machine learning model to determine a reference of a plurality of references that is closest to the crash signature and the crash configuration. The reference includes a reference crash signature and a reference configuration. The reference crash…
Josephson junction structures
Granted: July 16, 2024
Patent Number:
12041858
Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include alternating planar superconducting structures and planar non-superconducting structures arranged along a direction away from a wafer surface.
Memory safety interface configuration
Granted: July 16, 2024
Patent Number:
12038812
A memory safety interface module (MSIM) configured to test a memory. The MSIM receives an original data from a digital logic and inverts the bits of the original data to generate an inverted data. It writes the inverted data to the memory address. The MSIM reads the inverted data from the memory address and determines whether the memory address and the inverted data are correct. The MSIM either writes the original data to the memory address in response to the memory address and the…
Phase mismatch detection for a multiphase system
Granted: July 16, 2024
Patent Number:
12038780
A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple…
System and method for synchronizing net text across hierarchical levels
Granted: July 9, 2024
Patent Number:
12032894
A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the…
Throughput efficient Reed-Solomon forward error correction decoding
Granted: July 9, 2024
Patent Number:
12034458
A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap…
Fast effective resistance estimation using machine learning regression algorithms
Granted: July 9, 2024
Patent Number:
12032889
Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.
In-graph causality ranking for faults in the design of integrated circuits
Granted: July 9, 2024
Patent Number:
12032887
In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the…
Self-recovery mechanism for multi-hosts and multi-devices emulation and prototyping system bus
Granted: July 9, 2024
Patent Number:
12032510
A configuration to address a bus stall during data packet transmission also allows for bus recover due to data packet transmission errors. If a downstream node is not ready to receive data from a buffer of an upstream node, a timer counts a timeout value. The time count increments on each clock cycle in which the downstream node is not ready to receive data. The buffer is cleared at the upstream node when the count reaches a predetermined threshold value. Alternately, the configuration…
Accurate calibration of analog integrated-circuits continuous-time complex filters
Granted: July 2, 2024
Patent Number:
12028034
A first and second input tone are applied to a continuous-time complex filter within an integrated circuit. The magnitude of the output of the filter at the frequency of each of the first and second input tones are measured and compared to determine the value of a filter tuning control signal. A tuning control signal is applied to the filter with the determined value to tune the filter.
Memory optimization for storing objects in nested hash maps used in electronic design automation systems
Granted: July 2, 2024
Patent Number:
12026202
Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which…
Varied validity bit placement in tag bits of a memory
Granted: July 2, 2024
Patent Number:
12026094
A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.
Virtual isolated pattern layer: isolated pattern recognition, extraction and compression
Granted: June 25, 2024
Patent Number:
12019966
A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule…
Transforming a logical netlist into a hierarchical parasitic netlist
Granted: June 18, 2024
Patent Number:
12014127
A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on…
Testable time-to-digital converter
Granted: June 18, 2024
Patent Number:
12015411
A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of…
Advanced register merging
Granted: June 18, 2024
Patent Number:
12014205
Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for advanced register merging. A first register-merging operation may be configured to merge, into a first survivor register, a first plurality of registers of the RTL description. A second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency…
