Mask synthesis using tensor-based computing platforms
Granted: December 31, 2024
Patent Number:
12181793
A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further…
Automated translation of design specifications of electronic circuits
Granted: December 24, 2024
Patent Number:
12175191
Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target…
Timing-aware surgical optimization for engineering change order in chip design
Granted: December 24, 2024
Patent Number:
12175181
A method of performing an optimization within a circuit layout design is provided. The method includes determining, from multiple nets of the circuit layout design, a target net that has one or more performance characteristics that are outside a range of constraints, determining, from the multiple nets, a non-critical net that has the one or more performance characteristics that are within the range of the constraints, and adjusting, by a processor, one or more of a shape and a location…
Fast synthesis of logical circuit design with predictive timing
Granted: December 24, 2024
Patent Number:
12175176
A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to…
One-transistor (1T) one-time programmable (OTP) anti-fuse bitcell with reduced threshold voltage
Granted: December 10, 2024
Patent Number:
12167590
A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.
SRAM non-clamping write driver with write assist
Granted: December 10, 2024
Patent Number:
12165738
Various SRAM non-clamping write driver with write-assist are disclosed, including a write driver circuitry that does not clamp the Bitlines (BLs) during the write operations, and a negative BL Write-Assist (WA) circuit that provides a negative BL boost desirable for use with high-density bit cells. When used with memories other than those having high-density bit cells, the negative BL WA improves the minimum voltage (Vmin) and frequency of operation.
Obfuscating encrypted register transfer logic model of a circuit
Granted: December 10, 2024
Patent Number:
12164608
A method of obfuscating a circuit design includes, in part, receiving data representative of the circuit design. The method further includes, in part, simulating the circuit design, and obfuscating at least one output signal of the circuit design if a user performing the simulation is determined as not being an authorized user.
Power-efficient enable signal for fanin-based sequential clock gating on enabled flip flops
Granted: December 3, 2024
Patent Number:
12158770
A circuit includes, in part, first and second sequential elements and a clock gating circuit. The first sequential element has an enable terminal receiving a first enabling signal, a clock terminal receiving a first clock signal, a data input terminal and a data output terminal. The second sequential element has a clock terminal, and a data input terminal coupled to the data output terminal of the first sequential element. The clock gating circuit is coupled to the first and second…
Message passing multi processor network for simulation vector processing
Granted: November 26, 2024
Patent Number:
12153864
This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously…
Continuous time linear equalizer with programmable inductive high frequency boost
Granted: November 26, 2024
Patent Number:
12155509
A communication system includes a receiver device having a continuous time linear equalizer circuitry. The continuous time linear equalizer circuitry includes first gain circuitry, second gain circuitry, second gain circuitry a first capacitor, a first resistive element, a first inductor, and a second resistive element. The first gain circuitry and the second gain circuitry receive an input signal. The first capacitor is connected between an output of the first gain circuitry and an…
Multi-processor simulation on a multi-core machine
Granted: November 26, 2024
Patent Number:
12153863
The invention relates to methods of simulation of a plurality of processors running on a plurality of cores, to multi-core microprocessor systems in which such methods may be carried out, and to computer program products configured to perform a simulation of a plurality of processors, running on a plurality of cores. According to a first aspect of the invention, there is provided a method of running a plurality of simulated processors on a plurality of cores, in which simulation of the…
At-speed synchronous write-through operation for testing two-port memory
Granted: November 19, 2024
Patent Number:
12148490
A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is…
Co-optimizing power supply voltage in an integrated circuit design
Granted: November 19, 2024
Patent Number:
12147749
A relationship between at least a first metric of an integrated circuit (IC) design and a power supply voltage of the IC design may be determined based on a set of IC designs that have different power supply voltages. Next, the power supply voltage and at least the first metric of the IC design may be modified by interpolating values of the first metric based on the relationship between the first metric and the power supply voltage of the IC design.
System for making circuit design changes
Granted: November 19, 2024
Patent Number:
12147748
A system and method for changing a circuit design are described. The method includes generating a propagation graph for the circuit design and estimating slack values for some of the paths in the propagation graph. The method also includes making a virtual change to the circuit design and determining whether to accept or reject the change based on how the change affects the estimated slack values.
Buffer circuitry for store to load forwarding
Granted: November 19, 2024
Patent Number:
12147707
A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is…
Angle of arrival (AoA) determination for Bluetooth® Low Energy (BLE)
Granted: November 12, 2024
Patent Number:
12143195
A communication receiver can determine an angle of arrival (AoA) of a communication signal. The communication receiver includes multiple receiving antennas and processing circuitry. The processing circuitry determines multiple phase shifts over multiple instances in time from first samples of a communication signal as observed by a reference receiving antenna selected from among the multiple receiving antennas, samples the communication signal as observed by the selected receiving…
Device under test synchronization with automated test equipment check cycle
Granted: November 12, 2024
Patent Number:
12140632
Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the…
Integrating machine learning delay estimation in FPGA-based emulation systems
Granted: November 12, 2024
Patent Number:
12140628
A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays,…
Synchronization of a transfer of data signals between circuits when a clock in a destination circuit is off
Granted: October 29, 2024
Patent Number:
12130658
A method and system are provided for synchronizing signals, using a synchronizer circuit, between a source circuit and a destination circuit that utilizes detection of when the destination circuit clock is turned off. In the method performed by the synchronizer circuit, a stop signal is received from the destination circuit that is generated upon determination that the destination clock in the destination circuit is turned off. A data signal from the source circuit is, upon receipt of…
Power estimation using input vectors and deep recurrent neural networks
Granted: October 22, 2024
Patent Number:
12124780
A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a…
