Efficient realization of coverage collection in emulation
Granted: March 30, 2021
Patent Number:
10962595
Coverage event counters for hardware verification emulations are implemented as linear feedback shift register-based counters generating encoded counter values indicative of a detected number of coverage events. To decode those counter values, a counter algorithm utilized to generate the encoded counter value may continue to be iterated after counting is complete until reaching a defined pattern, while counting the number of iterations (K) necessary to reach the defined pattern. The…
Substrates and transistors with 2D material channels on 3D geometries
Granted: March 16, 2021
Patent Number:
10950736
Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit…
Hardware based state signature generation and check for test and debug of semiconductor circuit functionality
Granted: March 16, 2021
Patent Number:
10949591
A method of detecting a fault in a circuit design undergoing hardware emulation, includes, in part, comparing, in each cycle K of a clock and at the hardware emulation system, the cycle K register values of a reference circuit with the cycle K register values of the circuit design undergoing emulation. The method further includes detecting, in each cycle K of the clock and at the hardware emulation system, whether a mismatch exists between the cycle K reference circuit design register…
Method for compression of emulation time line in presence of dynamic re-programming of clocks
Granted: March 16, 2021
Patent Number:
10949589
The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further…
High speed, low hardware footprint waveform
Granted: March 16, 2021
Patent Number:
10949588
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces…
Clock and data recovery using closed-loop clock alignment and duplicate sampling clock
Granted: March 9, 2021
Patent Number:
10944406
A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed…
Managing resources for multiple trial distributed processing tasks
Granted: February 23, 2021
Patent Number:
10929177
A computer-implemented method of managing resources for multiple trial distributed processing tasks is presented. The method includes estimating an expected time needed to process each of a set of mask patterns which can be independently processed. The method further includes allocating each of the set of mask patterns to a set of processing cores in accordance with the expected time, and processing the mask patterns in accordance with the allocation, when the computer in invoked to…
Methodology using Fin-FET transistors
Granted: February 16, 2021
Patent Number:
10922467
A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate…
Dynamic bridging of interface protocols
Granted: February 16, 2021
Patent Number:
10922458
Systems and methods for protocol bridging for a system level modeling simulation (SLMS), such as a SYSTEMC simulation where the components communicate using a TLM2.0 application programming interface (API). The method includes accessing design configuration information describing a first component of the SLMS that uses a first communication protocol and a second component of the SLMS that uses a second communication protocol. Run-time bridging logic is inserted between the first…
Methodology to create constraints and leverage formal coverage analyzer to achieve faster code coverage closure for an electronic structure
Granted: February 9, 2021
Patent Number:
10915683
An efficient unreachability analysis tool utilizes toggle coverage report data to automatically generate constraints associated with viable constant signals (e.g., constant inputs, one-time programmable and constant registers) utilized in a circuit design before performing a full unreachability analysis process, thereby improving the functioning of the computer/processor executing the unreachability analysis process by identifying low-activity registers and constraining them before the…
Optical source compensation
Granted: February 9, 2021
Patent Number:
10915031
A method of compensating for degradation of an optical source includes in part, generating a first model of the optical source at a first point in time, generating a second model of the optical source at a second point in time occurring after the first point in time, determining the difference between the first and second models, and varying a dose of the optical source if the determined difference is greater than a first threshold value. The compensation method optionally includes, in…
Ground offset monitor and compensator
Granted: February 9, 2021
Patent Number:
10914762
Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known…
Creating and reusing customizable structured interconnects
Granted: February 2, 2021
Patent Number:
10909300
A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width,…
Reducing X-masking effect for linear time compactors
Granted: February 2, 2021
Patent Number:
10908213
A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains…
Detecting and displaying multi-patterning fix guidance
Granted: January 26, 2021
Patent Number:
10902176
A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
Connection and disconnection differential surge limiter circuit for AC coupled transceiver
Granted: January 26, 2021
Patent Number:
10901443
Disclosed herein are embodiments of a scalable connection and disconnection differential surge limiter circuit that may be utilized in any AC-coupled transceiver. Charge is recycled between PADP and PADN using two diode paths, hence protecting the PAD connected devices from voltage stress. The circuit can act as a protection circuit to limit the voltage on PADP and PADN during differential voltage spikes.
Netlist abstraction for circuit design floorplanning
Granted: January 19, 2021
Patent Number:
10896280
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
Extreme cases sampling method for improved variation-aware full custom design
Granted: January 19, 2021
Patent Number:
10896274
The independent claims of this patent signify a concise description of embodiments. Roughly described, disclosed is technology for yield improvement of an integrated circuit device implementing a circuit design which includes, in a first verification, verifying adherence of the circuit design to a set of performance specifications, over a first set of test cases which include variations in a fabrication process variable or an environmental condition. The verification includes…
User-defined rule engine
Granted: January 12, 2021
Patent Number:
10891410
In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph,…
Bit-line repeater insertion architecture
Granted: January 12, 2021
Patent Number:
10891992
An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.
