Fixing ESD path resistance errors in circuit design layout
Granted: January 5, 2021
Patent Number:
10885258
A physical verification tool for debugging ESD ground path resistance violations in ESD protection circuits. The ESD ground path is modeled and partitioned into component path structures (polygons) that are disposed in associated design layers. A total ESD ground path resistance is then calculated and compared with a maximum allowable resistance value defined by an ESD protection rule. When the ESD ground path is non-compliant, a resistance contribution ratio is determined for each…
Method for modeling glitches during circuit simulation
Granted: January 5, 2021
Patent Number:
10885248
Glitch propagation is modelled during circuit design simulation by determining the input duration of each signal pulse received by a cell, utilizing the input duration to distinguish whether the input pulse is a glitch or a valid data signal pulse, assigning a cell-type-specific scaling factor value to each signal pulse identified as a scalable glitch, calculating a scheduled output duration by multiplying the scaling factor value and the input duration, and controlling the cell by…
Self-organized snapping for repeater planning
Granted: December 29, 2020
Patent Number:
10878166
Techniques and systems for inserting repeaters in an integrated circuit (IC) design are described. Some embodiments can place a snapping region in the IC design, wherein the snapping region includes a predetermined arrangement of feasible grid regions and blocked grid regions, and wherein repeaters are allowed to be placed in feasible grid regions but not in blocked grid regions. Next, the embodiments can iteratively perform a set of operations, comprising: selecting a net from a set of…
Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference
Granted: December 29, 2020
Patent Number:
10878153
Apparatuses and methods for performing domain crossing verification of a register transfer level (RTL) representation of an integrated circuit (IC) that includes a memory block are provided. One example method includes receiving an RTL representation of an IC; automatically inferring one or more memory blocks in the RTL representation of the IC; identifying one or more input ports and one or more output ports of the one or more memory blocks; designating the one or more input ports and…
Machine learning based power optimization using parallel training and localized data generation
Granted: December 15, 2020
Patent Number:
10867091
A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying…
One-time programmable (OTP) anti-fuse memory cell
Granted: December 15, 2020
Patent Number:
10867674
A memory storage device is disclosed herein which having volatile memory cells and non-volatile memory cells. The memory storage device can be implemented within a portable electronic device. These portable electronic devices often load data from non-volatile memory cells into volatile memory cells, for example, upon powering up. Conventionally, portable electronic devices often include separate non-volatile memory storage devices and volatile memory storage devices which requires a…
Reset before write architecture and method
Granted: December 15, 2020
Patent Number:
10867665
An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range.
Routing for length-matched nets in interposer designs
Granted: December 15, 2020
Patent Number:
10867106
Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same…
Real-time interactive routing using topology-driven line probing
Granted: December 15, 2020
Patent Number:
10867105
Techniques and systems for determining a route from a start point to a target point in an integrated circuit (IC) design using topology-driven line probing are described. Some embodiments can create a data structure to store a set of nodes, wherein each node is located on a horizontal probe or a vertical probe, and wherein each node has a cost. The embodiments can then perform a set of operations in an iterative loop, the set of operations comprising: selecting a lowest cost node from…
Elmore delay time (EDT)-based resistance model
Granted: December 15, 2020
Patent Number:
10867097
We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal…
Selective execution for partitioned parallel simulations
Granted: December 1, 2020
Patent Number:
10853544
Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a…
Compact modeling for the negative tone development processes
Granted: December 1, 2020
Patent Number:
10852635
A photolithography model used in an optical proximity correction process modifies an image output intensity of a point disposed along a two dimensional plane and having coordinates (x,y) in accordance with a gradient of a convolution of a mask value at the point and a sampling pattern function selected at the point. The sampling pattern function includes, in part, a first subset of sampling patterns and a second subset of sampling patterns. The first subset of sampling patterns includes…
Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on neural networks
Granted: November 24, 2020
Patent Number:
10846591
A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for CNN applications that may be…
Automatic definition and extraction of functional coverage metric for emulation-based verification
Granted: November 24, 2020
Patent Number:
10846455
A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the…
Generating interrelated path groups by using machine learning
Granted: November 24, 2020
Patent Number:
10846453
Techniques and systems for generating path groups for a set of violating timing path end-points in an integrated circuit (IC) design are described. Some embodiments can determine a set of attribute values for each violating timing path end-point in a set of violating timing path end-points. Next, the embodiments can use an unsupervised machine learning clustering technique to determine a set of clusters by using the attribute values. The embodiments can then generate a path group for…
Robust exclusive sum-of-product (ESOP) refactoring
Granted: November 17, 2020
Patent Number:
10839117
Robust logic optimization on an IC design based on exclusive sum-of-products (ESOP) refactoring is described. ESOP expressions are two-level logic representation forms, similar to sum-of-product SOP representations. However, since ESOPs use exclusive-OR (XOR) instead of OR operators they can be exponentially more compact than sum-of-product (SOP) expressions for important classes of functions. In XOR heavy logic, ESOP expressions allow us to find optimizations that SOPs simply do not…
Efficient execution of alternating automaton representing a safety assertion for a circuit
Granted: November 10, 2020
Patent Number:
10831956
A system receive as input a circuit design and a description of the behavior of the circuit design specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. The system generates an alternating automaton representing the assertions. The alternating automaton may be non-deterministic. The system translates the alternating automaton to a finite state machine (FSM) that may be represented using a representation such as…
Reconfigurable connections
Granted: November 10, 2020
Patent Number:
10831968
An improved placement and routing method for circuit simulation includes receiving setup input controls to set up an initial arrangement of two blocks (e.g., a synthesized block and an IP block), and a designation of permutable interconnections; performing permutations of permutable interconnect signals on the, e.g., design block (or any other block)-IP block arrangement to determine an optimal permutation; compiling a bitstream comprising a final placement and route of a circuit based…
Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data
Granted: November 10, 2020
Patent Number:
10831961
A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional…
Simulation scaling with DFT and non-DFT
Granted: November 10, 2020
Patent Number:
10831957
Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
