Simulation scaling with DFT and non-DFT
Granted: November 10, 2020
Patent Number:
10831957
Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
Efficient execution of alternating automaton representing a safety assertion for a circuit
Granted: November 10, 2020
Patent Number:
10831956
A system receive as input a circuit design and a description of the behavior of the circuit design specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. The system generates an alternating automaton representing the assertions. The alternating automaton may be non-deterministic. The system translates the alternating automaton to a finite state machine (FSM) that may be represented using a representation such as…
High performance and low power TSPC latch with data agnostic setup and hold time
Granted: November 3, 2020
Patent Number:
10826469
A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate…
Voltage drop assisted power-grid augmentation
Granted: October 27, 2020
Patent Number:
10817645
A method for reducing voltage hot spots in a power grid for a circuit design is implemented on a computer system and includes the following steps. The computer system (e.g., an EDA tool) accesses the circuit design. The circuit design includes a power grid that distributes power throughout the circuit design. The computer system identifies spots in the power grid with excessive voltage drops. These will be referred to as hot spots. The power grid is augmented by adding local conductors…
Systems and methods for reserving IC design spacing for power net routing
Granted: October 27, 2020
Patent Number:
10817642
Various embodiments are directed to a mechanism for reserving power resources to address non-uniform and complex routings on a redistribution layer of a flip-chip. Reserving power resources may be performed by rerouting RDL nets by, for example, identifying an initial RDL net route for a RDL net; defining an outer boundary relative to the initial RDL net route, wherein a perimeter of the outer boundary is defined at a defined distance away from the initial RDL net route; defining one or…
Transparent hierarchical routing in an integrated circuit design
Granted: October 27, 2020
Patent Number:
10817639
Systems and techniques are described for transparent hierarchical routing in an integrated circuit (IC) design. A logical netlist can be analyzed in the IC design to identify endpoints of a physical route that crosses at least one physical hierarchy boundary. Next, a set of routing shapes can be created to electrically connect the endpoints of the physical route. The set of routing shapes can then be transformed to corresponding routing shapes in each physical hierarchy context along the…
Methodology using Fin-FET transistors
Granted: October 27, 2020
Patent Number:
10817636
A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and…
Machine-learning circuit optimization using quantized prediction functions
Granted: October 27, 2020
Patent Number:
10817634
An EDA tool trains a machine-learning optimization tool using quantized optimization solution (training) data generated by conventional optimization tools. Each training data entry includes an input vector and an associated output vector that have quantized component values respectively determined by associated operating characteristics of initial (non-optimal) and corresponding replacement (optimized) circuit portions, where each initial circuit portion is identified and replaced by the…
Determination of dimensional changes of features across mask pattern simulation fields
Granted: October 20, 2020
Patent Number:
10810339
A method of determining dimensional changes of features in a mask involves calculating a spacing to be used between adjacent unit cells, correcting a unit cell surrounded by replicas of the same unit cell at the calculated spacing for optical proximity effects, arraying the proximity corrected unit cell at the calculated spacing, and dividing the array of unit cells into templates. Each template frames a portion of the array of unit cells, and locations of the unit cells in each framed…
Phase-aware control and scheduling
Granted: October 13, 2020
Patent Number:
10803000
Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to…
Two-part interface PHY for system-on-chip devices
Granted: October 13, 2020
Patent Number:
10802566
A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low…
Full-custom voltage-dependent design rules (VDRC) flow
Granted: October 6, 2020
Patent Number:
10796062
The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool. Various embodiments include at least a computer-implemented method of performing Voltage-based Design Rule Checking (VDRC) in a full-custom EDA Design and Implementation Platform is provided, the method comprising receiving a plurality of…
Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator
Granted: October 6, 2020
Patent Number:
10796048
The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second…
Multi-protocol receiver
Granted: September 29, 2020
Patent Number:
10791203
A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to…
Read-write architecture for low voltage SRAMs
Granted: September 29, 2020
Patent Number:
10790013
An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
Method and apparatus for SOC with optimal RSMA
Granted: September 29, 2020
Patent Number:
10789398
A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.
DRC processing tool for early stage IC layout designs
Granted: September 22, 2020
Patent Number:
10783311
A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined…
Analyzing delay variations and transition time variations for electronic circuits
Granted: September 22, 2020
Patent Number:
10783301
A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing…
Efficient lattice kinetic monte carlo simulations for epitaxial growth
Granted: September 15, 2020
Patent Number:
10776539
A method for simulating an epitaxial process in a body having a crystal lattice structure. Roughly described, an enlarged version of the crystal lattice structure is formed, having a lattice constant increased by a lattice enlargement factor N>1. The subject fabrication process is simulated by a Lattice Kinetic Monte Carlo algorithm in which various factors have been scaled in accordance with N. The simulation speed increases by a factor around N3, without significantly degrading the…
Nano-wire resistance model
Granted: September 15, 2020
Patent Number:
10776552
An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as…
