Mapping intermediate material properties to target properties to screen materials
Granted: September 15, 2020
Patent Number:
10776560
A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and…
Nano-wire resistance model
Granted: September 15, 2020
Patent Number:
10776552
An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as…
Efficient lattice kinetic monte carlo simulations for epitaxial growth
Granted: September 15, 2020
Patent Number:
10776539
A method for simulating an epitaxial process in a body having a crystal lattice structure. Roughly described, an enlarged version of the crystal lattice structure is formed, having a lattice constant increased by a lattice enlargement factor N>1. The subject fabrication process is simulated by a Lattice Kinetic Monte Carlo algorithm in which various factors have been scaled in accordance with N. The simulation speed increases by a factor around N3, without significantly degrading the…
Method for cycle accurate data transfer in a skewed synchronous clock domain
Granted: September 15, 2020
Patent Number:
10775836
A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge,…
Predicting no-defect-found physical failure analysis results using Bayesian inference and generalized linear models
Granted: September 8, 2020
Patent Number:
10769347
A Physical Fault Analysis (PFA) outcome prediction tool utilizes previously-generated evaluation data and associated PFA outcome data to generate a Bayesian Generalized Linear Model (BGLM), and then utilizes the BGLM to generate a PFA outcome prediction for newly-submitted evaluation data that operably characterizes measured operating characteristics of an IC chip that is being developed. The BGLM generation methodology by utilizing a Generalized Linear Model (GLM) in a Bayesian…
Local band-to-band-tunneling model for TCAD simulation
Granted: September 8, 2020
Patent Number:
10769339
An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1…
Retention model with RTL-compatible default operating mode
Granted: September 8, 2020
Patent Number:
10769329
A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the…
Method and apparatus for increasing the number of USB root hub ports
Granted: September 1, 2020
Patent Number:
10762018
Various embodiments are directed to a USB hub configured for supporting multiple data transfer speed protocols. The USB hub comprises a plurality of protocol/LINK layer components; and a physical layer component shared among the plurality of protocol/LINK layer components and supporting at least two USB connection ports. The physical layer component is in communication with each of the plurality of protocol/LINK layer components. A buffer system (including RX/TX buffers) is shared among…
Circuitry and method for dual mode reed-solomon-forward error correction decoder
Granted: September 1, 2020
Patent Number:
10763895
A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an…
Multi-dimensional constraint solver using modified relaxation process
Granted: September 1, 2020
Patent Number:
10762262
A constraint solver utilizes a modified relaxation process to generate multiple different stimulus stream arrays that comply with multi-dimensional (e.g., 2D or 3D) constraints. First, an array is generated including rows and columns of randomly generated test vector values. During a first revision phase, the array is modified to comply with first-dimension constraints (e.g., selected test vector values are changed in non-compliant rows until every row complies with all row constraints).…
FinFET with heterojunction and improved channel control
Granted: August 25, 2020
Patent Number:
10756212
Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first…
Circuit design including design rule violation correction utilizing patches based on deep reinforcement learning
Granted: August 25, 2020
Patent Number:
10755026
A method of improving a design rule fixing process comprises receiving an integrated circuit design, including layout elements, and identifying a plurality of design rule violations in the integrated circuit design. The process then identifies a plurality of possible actions, each action comprising fixing a design rule. The process then uses a deep learning algorithm to select an action, the action representing fixing of a particular design rule violation. The process then comprises…
Circuit timing analysis
Granted: August 25, 2020
Patent Number:
10755023
An arrival time propagation method and system for statistical circuit analysis that uses a conjugation operation and a negation operation to determine and adjust arrival times in a circuit model and to determine path ordering in a circuit.
Multi-modulus frequency divider circuit
Granted: August 18, 2020
Patent Number:
10749531
A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the…
Parameter generation for modeling of process-induced semiconductor device variation
Granted: August 18, 2020
Patent Number:
10747916
A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of coordinates in a process space with dimensions of process-dependent device parameters Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the coordinates in the process space. Statistics of the extracted model parameters…
System and method for cryptographic processing in a time window
Granted: August 11, 2020
Patent Number:
10740497
A method is disclosed for providing first data and a first secret key to a cipher processor for ciphering. The first data is ciphered in accordance with a first cipher process and the first secret key to provide output data. Before ciphering of the first data, extra data is inserted within the cipher processor for ciphering in accordance with at least a portion of said first cipher process. The extra data is inserted within a sequence of cipher processor operations for obfuscating the…
Method and apparatus for floating or applying voltage to a well of an integrated circuit
Granted: August 11, 2020
Patent Number:
10741538
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…
Semiconductor device simulation
Granted: August 11, 2020
Patent Number:
10740525
A method for simulating semiconductor devices includes running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results. Mobility parameters are extracted across the DoE space from the EMC results. A response-surface mobility model is constructed using the extracted mobility parameters. The response-surface mobility model is used to run a drift-diffusion…
Pessimism in static timing analysis
Granted: August 11, 2020
Patent Number:
10740520
The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at…
Integrated circuit (IC) optimization using Boolean resynthesis
Granted: August 11, 2020
Patent Number:
10740517
Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a…
