Integrated circuit (IC) optimization using Boolean resynthesis
Granted: August 11, 2020
Patent Number:
10740517
Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a…
System and method for cryptographic processing in a time window
Granted: August 11, 2020
Patent Number:
10740497
A method is disclosed for providing first data and a first secret key to a cipher processor for ciphering. The first data is ciphered in accordance with a first cipher process and the first secret key to provide output data. Before ciphering of the first data, extra data is inserted within the cipher processor for ciphering in accordance with at least a portion of said first cipher process. The extra data is inserted within a sequence of cipher processor operations for obfuscating the…
Atomic structure optimization
Granted: August 4, 2020
Patent Number:
10734097
Computer system provided with a control module for controlling ab initio atomic structure modules for simulating the behavior of structures and materials at multiple scales with different modules, for purposes of evaluating such structures and materials for use in integrated circuit devices. The computer system can simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.
Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
Granted: August 4, 2020
Patent Number:
10733348
Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least…
System and method for hierarchical power verification
Granted: August 4, 2020
Patent Number:
10733342
A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include…
Method for calibrating the read latency of a DDR DRAM module
Granted: July 28, 2020
Patent Number:
10725681
A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value.…
Method and framework to dynamically split a testbench into concurrent simulatable multi-processes and attachment to parallel processes of an accelerated platform
Granted: July 21, 2020
Patent Number:
10719644
The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel.…
Spine routing and pin grouping with multiple main spines
Granted: July 21, 2020
Patent Number:
10719653
A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire…
Hierarchical dynamic heat maps in full custom EDA applications
Granted: July 21, 2020
Patent Number:
10719650
Systems and method for generating graphical visualizations of an integrated circuit (IC) design may comprise configurations for generating interactive graphical visualizations of the IC design configured for providing informative overlays to the graphical visualizations based on a selected zoom level of the graphical visualization. In certain embodiments, the graphical overlays may be generated over corresponding objects for providing information regarding hierarchies of objects, or for…
Speed converter for FPGA-based UFS prototypes
Granted: July 21, 2020
Patent Number:
10719647
A method for generating FPGA-based prototype systems capable of implementing UFS HS-G4 communication protocols using inexpensive/slow FPGAs. ASIC/SoC-targeted circuit designs are modified to include a speed converter that causes a UFS controller to generate transmitted data streams at one-half operating speed (e.g., 146 MHz) during HS-G4 operations, modifies the transmitted data streams to intersperse filler data values between transmitted data values, and transmits the modified data…
Phase-locked loop (PLL) with calibration circuit
Granted: July 14, 2020
Patent Number:
10715158
A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the…
PUF latch for OTP memory arrays and method of operation
Granted: July 14, 2020
Patent Number:
10714199
A physical unclonable function (PUF) circuit generates one or more bit values. The PUF circuit includes a first one-time programmable (OTP) memory cell, a second OTP memory cell, and a latch circuit connected to the first and second OTP memory cells. The latch circuit initiates programming of the first and second OTP memory cells, detects a faster programming OTP memory cell of the first and second OTP memory cells, inhibits programming of a slower programming OTP memory cell of the…
Parameter generation for semiconductor device trapped-charge modeling
Granted: July 14, 2020
Patent Number:
10713405
A method for generating semiconductor device model parameters includes receiving semiconductor device performance data of statistical instances of semiconductor devices, for a plurality of areal trapped charge densities Model parameters are extracted to produce individual model instances, each corresponding to the respective statistical instances for the areal trapped charge densities. Statistics of the extracted model parameters are modeled by processing the individual model instances…
Software and hardware emulation system
Granted: July 14, 2020
Patent Number:
10713069
A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. The method further comprising, when the system has not performed to the specification, determining one or more of the hardware and software portions to update for…
Method and apparatus for integrated level-shifter and memory clock
Granted: July 7, 2020
Patent Number:
10706916
An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a…
Estimation of effective channel length for FinFETs and nano-wires
Granted: July 7, 2020
Patent Number:
10706209
Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant…
Voltage reconciliation in multi-level power managed systems
Granted: July 7, 2020
Patent Number:
10706192
A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both…
On-chip heating and self-annealing in FinFETs with anti-punch-through implants
Granted: June 30, 2020
Patent Number:
10699914
The independent claims of this patent signify a concise description of the embodiments. Disclosed is technology for reducing transistor degradations by annealing through heat generated by anti-punch-through implants of the transistors. A first and second electrically conductive pillars are disposed on top a well hosting the transistors. A voltage applied across the first and second pillars enable the anti-punch-through implants to generate heat for the annealing process.
Identifying root cause of layout versus schematic errors
Granted: June 23, 2020
Patent Number:
10691867
A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values…
Multi-scale simulation including first principles band structure extraction
Granted: June 16, 2020
Patent Number:
10685156
Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract…
