Machine learning based parasitic estimation for an integrated circuit chip design
Granted: December 5, 2023
Patent Number:
11836435
Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of…
Memory instance reconfiguration using super leaf cells
Granted: December 5, 2023
Patent Number:
11836433
A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected…
Engineering change orders with consideration of adversely affected constraints
Granted: December 5, 2023
Patent Number:
11836425
In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related…
Automatic global clock tree synthesis
Granted: December 5, 2023
Patent Number:
11836000
A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second…
System and method for automatically capturing source code and associated artifacts for static analysis
Granted: November 28, 2023
Patent Number:
11829751
This disclosure describes a system and method of automatically capturing source code and associated artifacts for static analysis. A method includes receiving a current state of a project that includes a set of files in a directory to be captured for analysis and a current capture status of individual files of the set of files, determining a plan including a sequence of actions in response to the current state of the project, and executing the sequence of actions to capture each of the…
Guided power grid augmentation system and method
Granted: November 28, 2023
Patent Number:
11829698
A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum…
Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)
Granted: November 28, 2023
Patent Number:
11829692
Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case…
Clock multiplexer circuitry with glitch reduction
Granted: November 21, 2023
Patent Number:
11824539
Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and…
Dose information generation and communication for lithography manufacturing systems
Granted: November 21, 2023
Patent Number:
11822232
A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask…
Strongly connected component (SCC) graph representation for interactive analysis of overlapping loops in emulation and prototyping
Granted: November 14, 2023
Patent Number:
11816409
Embodiments relate to a system and method for analyzing strongly connected components (SCCs) in a design of an integrated circuit. In one embodiment, a design of an integrated circuit is received, and a set of loops are identified in the received design. Based on the identified loops, one or more SCCs are determined. Each SCC includes multiple loops having shared paths. For instance, an SCC includes a first loop having a first set of nodes connected via a first set of paths and a second…
Automatic channel identification of high-bandwidth memory channels for auto-routing
Granted: November 14, 2023
Patent Number:
11816407
Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method…
Debug methodology for a USB sub-system using unique identifier (UID) approach
Granted: November 7, 2023
Patent Number:
11809363
A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block,…
Freeform optical surface and method of forming a freeform optical surface
Granted: October 31, 2023
Patent Number:
11803051
A freeform optical surface includes, in part, an off-axis optical surface and a departure optical module. The off-axis optical surface may be an off-axis conic optical surface. The departure optical module may be substantially perpendicular to the off-axis conic optical surface.
Compiler-based code generation for post-silicon validation
Granted: October 24, 2023
Patent Number:
11796593
Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon…
Scalable supply multiplexer circuit
Granted: October 24, 2023
Patent Number:
11799480
A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning…
Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design
Granted: October 24, 2023
Patent Number:
11797742
A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value…
Endpoint path margin based integrated circuit design using sub-critical timing paths
Granted: October 24, 2023
Patent Number:
11797739
Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing…
Finding equivalent classes of hard defects in stacked MOSFET arrays
Granted: October 24, 2023
Patent Number:
11797737
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the…
Regression testing based on overall confidence estimating
Granted: October 24, 2023
Patent Number:
11797735
A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results,…
Single-pass diagnosis for multiple chain defects
Granted: October 17, 2023
Patent Number:
11789077
Disclosed herein are method, system, and storage-medium embodiments for single-pass diagnosis of multiple chain defects in circuit-design testing. Embodiments include processor(s) to select a plurality of a scan chains in a circuit under test and determine presence of at least a first defect in the first scan chain, and a second defect in the first scan chain or in the second scan chain. The plurality of scan chains may include specific scan chains that each have respective pluralities…
