Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis
Granted: October 22, 2024
Patent Number:
12124782
A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.
Power estimation using input vectors and deep recurrent neural networks
Granted: October 22, 2024
Patent Number:
12124780
A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a…
Management circuitry for a least recently used memory management process
Granted: October 22, 2024
Patent Number:
12124379
A processing system employs a method to order the elements within a memory. Ordering the elements includes receiving an accessed memory element. The accessed memory element is requested by a processor from a memory. Further, the accessed memory element is compared to stored elements within the memory to generate control signals. Gate control signals from the control signals are generated. The order of the stored elements within the memory is updated based on the gate control signals.
Predicting aliasing bits in a virtually indexed physically tagged cache
Granted: October 22, 2024
Patent Number:
12124375
A second virtual address may be received, where the second virtual address is different from a first virtual address. A second hash value may be computed based on the second virtual address. A first comparison result may be determined by comparing the second hash value with a first hash value, where the first hash value is computed based on the first virtual address. The first comparison result may be used to select a selected structure from either a first structure or a second…
Clock synthesizer with dual control
Granted: October 15, 2024
Patent Number:
12119828
The present disclosure describes circuits (e.g., clock synthesizers) and methods for producing alternating signals. A clock synthesizer includes an oscillator, a voltage control circuit, and a frequency control circuit. The oscillator produces an output signal with a frequency. The voltage control circuit produces a control voltage for the oscillator based on the frequency of the output signal. The frequency control circuit produces a control signal for the oscillator based on (i) an…
Glitch filter with reset circuit
Granted: October 15, 2024
Patent Number:
12119827
An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the…
Automatic channel identification of high-bandwidth memory channels for auto-routing
Granted: October 15, 2024
Patent Number:
12118283
Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method…
Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
Granted: October 15, 2024
Patent Number:
12117488
A system and method are provided for testing logic using a logic built in self-test (LBIST) system, and in particular where the LBIST system tolerates unknown inputs (Xs) to the logic cells forming an XLBIST system. The system allows for providing multiple test system clocks from the LBIST system to the logic during a system clock capture cycle of a system clock during testing of the logic, wherein the system clock is separate from the multiple test system clocks of the LBIST system.…
Framework for application driven exploration and optimization of hardware engines
Granted: October 8, 2024
Patent Number:
12112202
A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first…
Scan chain compression for testing memory of a system on a chip
Granted: October 8, 2024
Patent Number:
12112818
A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer…
Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation
Granted: October 8, 2024
Patent Number:
12112108
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
Memory efficient and scalable approach to stimulus (waveform) reading
Granted: October 1, 2024
Patent Number:
12106157
Embodiments relate to reading signals from a stimulus file produced by an emulator into a data store. A method includes executing, by a set of one or more worker processes, reading tasks. Each reading task is executable independent of other reading tasks. Each reading task includes reading a time slice of a signal from a stimulus file produced by a hardware emulator, and pushing a partial waveform corresponding to the time slice to a data store. The partial waveform includes a head and a…
Using multiple error correction code decoders to store extra data in a memory system
Granted: September 17, 2024
Patent Number:
12095474
Disclosed is a configuration to store metadata using an error correction code (ECC). The configuration receives at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0. The configuration generates a meta symbol using the N-bit metadata and creates an enhanced write data, the enhanced write data comprising the write data and the meta symbol generated by the N-bit metadata. The configuration encodes the enhanced write data and meta…
Diagnosing faults in memory periphery circuitry
Granted: September 17, 2024
Patent Number:
12094548
Methods for diagnosing faults in memory periphery circuitry, computer readable media, and a test device for the same are provided. In one example, method is provided that includes receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, and wherein the first test process is associated with a first circuit…
Power supply tracking circuitry for embedded memories
Granted: September 17, 2024
Patent Number:
12094513
Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted…
Multi-cycle power analysis of integrated circuit designs
Granted: September 17, 2024
Patent Number:
12093620
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with…
Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries
Granted: September 10, 2024
Patent Number:
12086523
A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes…
High-voltage IO drivers
Granted: September 10, 2024
Patent Number:
12085970
A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to…
On-the-fly multi-bit flip flop generation
Granted: September 3, 2024
Patent Number:
12079558
On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.
One time programmable bitcell with select device in isolated well
Granted: September 3, 2024
Patent Number:
12082403
A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M?1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further…
