On-the-fly multi-bit flip flop generation
Granted: September 3, 2024
Patent Number:
12079558
On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.
Fail-safe protection architecture for high voltage tolerant input/output circuit
Granted: August 27, 2024
Patent Number:
12074597
A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high…
High-voltage tolerant multiplexer
Granted: August 27, 2024
Patent Number:
12074593
A differential multiplexer includes a number of input stages. Each stage includes, in part, first and second transistor receiving an input signal and the inverse of the input signal, a biasing circuit supplying a bias to the gate terminal of the first and second transistors, a current source coupled between a source terminal of the first and second transistors and a ground terminal, a first switch coupling a drain terminal of the first transistor to a first terminal of a first resistor…
Memory clock level-shifting buffer with extended range
Granted: August 27, 2024
Patent Number:
12073876
A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first…
Propagating physical design information through logical design hierarchy of an electronic circuit
Granted: August 27, 2024
Patent Number:
12073156
A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design.…
Hardware-based obfuscation of digital data
Granted: August 20, 2024
Patent Number:
12067091
Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes…
Complementary single-ended to differential converter with weighed interpolation
Granted: August 6, 2024
Patent Number:
12057840
A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third…
Common mode logic based quadrature coupled injection locked frequency divider with internal power-supply jitter compensation
Granted: August 6, 2024
Patent Number:
12057839
A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of…
Automatic tracking for clock synchronization based on delay line adjustment
Granted: July 30, 2024
Patent Number:
12051481
A method includes: receiving a data signal (DQ) and a clock signal (DQS); generating an indicator signal by: delaying the data signal (DQ) to generate a delayed data signal (DQ?); sampling the data signal (DQ) and the delayed data signal (DQ?) using an edge of the clock signal (DQS) to generate a first sampled value and a second sampled value; and generating the indicator signal based on the first sampled value and the second sampled value; and adjusting one or more of a DQ adjustable…
Conversion of a clean unique request to a read unique request by a memory coherency manager circuit
Granted: July 23, 2024
Patent Number:
12045167
A system and method mitigates conflicts between clean unique requests by receiving a first clean unique request from a first processor core and a second clean unique request from a second processor core. The first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory. The memory is coupled to the first processor core and the second processor core. The first clean…
Test case selection and ordering with covert minimum set cover for functional qualification
Granted: July 23, 2024
Patent Number:
12045158
Techniques and systems for test case selection and ordering with covert minimum set cover for functional qualification are described. Some embodiments can determine a first set of test cases by, iteratively, identifying a set of faults that is covered by a smallest set of test cases, determining whether or not a test case that covers a fault is able to detect the fault, and selecting and adding a test case to the first set of test cases. Next, the embodiments can execute a minimum set…
Machine learning technique to diagnose software crashes
Granted: July 23, 2024
Patent Number:
12045124
A method includes receiving a crash signature and a crash configuration. The crash signature is generated in response to a software crash in a software application caused by the crash configuration. The method also includes applying a first machine learning model to determine a reference of a plurality of references that is closest to the crash signature and the crash configuration. The reference includes a reference crash signature and a reference configuration. The reference crash…
Josephson junction structures
Granted: July 16, 2024
Patent Number:
12041858
Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include alternating planar superconducting structures and planar non-superconducting structures arranged along a direction away from a wafer surface.
Memory safety interface configuration
Granted: July 16, 2024
Patent Number:
12038812
A memory safety interface module (MSIM) configured to test a memory. The MSIM receives an original data from a digital logic and inverts the bits of the original data to generate an inverted data. It writes the inverted data to the memory address. The MSIM reads the inverted data from the memory address and determines whether the memory address and the inverted data are correct. The MSIM either writes the original data to the memory address in response to the memory address and the…
Phase mismatch detection for a multiphase system
Granted: July 16, 2024
Patent Number:
12038780
A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple…
Self-recovery mechanism for multi-hosts and multi-devices emulation and prototyping system bus
Granted: July 9, 2024
Patent Number:
12032510
A configuration to address a bus stall during data packet transmission also allows for bus recover due to data packet transmission errors. If a downstream node is not ready to receive data from a buffer of an upstream node, a timer counts a timeout value. The time count increments on each clock cycle in which the downstream node is not ready to receive data. The buffer is cleared at the upstream node when the count reaches a predetermined threshold value. Alternately, the configuration…
Throughput efficient Reed-Solomon forward error correction decoding
Granted: July 9, 2024
Patent Number:
12034458
A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap…
System and method for synchronizing net text across hierarchical levels
Granted: July 9, 2024
Patent Number:
12032894
A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the…
Fast effective resistance estimation using machine learning regression algorithms
Granted: July 9, 2024
Patent Number:
12032889
Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.
In-graph causality ranking for faults in the design of integrated circuits
Granted: July 9, 2024
Patent Number:
12032887
In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the…
